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git01.mediatek.com / filogic / uboot / f6625b43ef2fb5f44e4e341317ab932f953ae39e / . / arch / x86 / dts / cherryhill.dts
blob: 37146fde2ba93aff7b03f94e52930b8ed90fe23d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]2/*
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]4 */
5
6/dts-v1/;
7
8#include <asm/arch-braswell/fsp/fsp_configs.h>
9#include <dt-bindings/interrupt-router/intel-irq.h>
10
11/include/ "skeleton.dtsi"
12/include/ "serial.dtsi"
Bin Mengaf5b8d22018-07-19 03:07:33 -0700[diff] [blame]13/include/ "reset.dtsi"
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]14/include/ "rtc.dtsi"
15/include/ "tsc_timer.dtsi"
16
17/ {
18 model = "Intel Cherry Hill";
19 compatible = "intel,cherryhill", "intel,braswell";
20
21 aliases {
22 serial0 = &serial;
23 spi0 = &spi;
24 };
25
26 config {
27 silent_console = <0>;
28 };
29
30 chosen {
31 stdout-path = "/serial";
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame]40 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]41 reg = <0>;
42 intel,apic-id = <0>;
43 };
44
45 cpu@1 {
46 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame]47 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]48 reg = <1>;
49 intel,apic-id = <2>;
50 };
51
52 cpu@2 {
53 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame]54 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]55 reg = <2>;
56 intel,apic-id = <4>;
57 };
58
59 cpu@3 {
60 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame]61 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]62 reg = <3>;
63 intel,apic-id = <6>;
64 };
65 };
66
67 pci {
68 compatible = "pci-x86";
69 #address-cells = <3>;
70 #size-cells = <2>;
71 u-boot,dm-pre-reloc;
72 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
73 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
74 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
75
76 pch@1f,0 {
77 reg = <0x0000f800 0 0 0 0>;
78 compatible = "intel,pch9";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]79
80 irq-router {
81 compatible = "intel,irq-router";
82 intel,pirq-config = "ibase";
83 intel,ibase-offset = <0x50>;
84 intel,pirq-link = <8 8>;
85 intel,pirq-mask = <0xdee0>;
86 intel,pirq-routing = <
87 /* Braswell PCI devices */
88 PCI_BDF(0, 2, 0) INTA PIRQA
89 PCI_BDF(0, 3, 0) INTA PIRQA
90 PCI_BDF(0, 11, 0) INTA PIRQA
91 PCI_BDF(0, 16, 0) INTA PIRQA
92 PCI_BDF(0, 17, 0) INTA PIRQA
93 PCI_BDF(0, 18, 0) INTA PIRQA
94 PCI_BDF(0, 19, 0) INTA PIRQA
95 PCI_BDF(0, 20, 0) INTA PIRQA
96 PCI_BDF(0, 21, 0) INTA PIRQA
97 PCI_BDF(0, 24, 0) INTA PIRQA
98 PCI_BDF(0, 24, 1) INTC PIRQC
99 PCI_BDF(0, 24, 2) INTD PIRQD
100 PCI_BDF(0, 24, 3) INTB PIRQB
101 PCI_BDF(0, 24, 4) INTA PIRQA
102 PCI_BDF(0, 24, 5) INTC PIRQC
103 PCI_BDF(0, 24, 6) INTD PIRQD
104 PCI_BDF(0, 24, 7) INTB PIRQB
105 PCI_BDF(0, 26, 0) INTA PIRQA
106 PCI_BDF(0, 27, 0) INTA PIRQA
107 PCI_BDF(0, 28, 0) INTA PIRQA
108 PCI_BDF(0, 28, 1) INTB PIRQB
109 PCI_BDF(0, 28, 2) INTC PIRQC
110 PCI_BDF(0, 28, 3) INTD PIRQD
111 PCI_BDF(0, 30, 0) INTA PIRQA
112 PCI_BDF(0, 30, 3) INTA PIRQA
113 PCI_BDF(0, 30, 4) INTA PIRQA
114 PCI_BDF(0, 31, 0) INTB PIRQB
115 PCI_BDF(0, 31, 3) INTB PIRQB
116
117 /*
118 * PCIe root ports downstream
119 * interrupts
120 */
121 PCI_BDF(1, 0, 0) INTA PIRQA
122 PCI_BDF(1, 0, 0) INTB PIRQB
123 PCI_BDF(1, 0, 0) INTC PIRQC
124 PCI_BDF(1, 0, 0) INTD PIRQD
125 PCI_BDF(2, 0, 0) INTA PIRQB
126 PCI_BDF(2, 0, 0) INTB PIRQC
127 PCI_BDF(2, 0, 0) INTC PIRQD
128 PCI_BDF(2, 0, 0) INTD PIRQA
129 PCI_BDF(3, 0, 0) INTA PIRQC
130 PCI_BDF(3, 0, 0) INTB PIRQD
131 PCI_BDF(3, 0, 0) INTC PIRQA
132 PCI_BDF(3, 0, 0) INTD PIRQB
133 PCI_BDF(4, 0, 0) INTA PIRQD
134 PCI_BDF(4, 0, 0) INTB PIRQA
135 PCI_BDF(4, 0, 0) INTC PIRQB
136 PCI_BDF(4, 0, 0) INTD PIRQC
137 >;
138 };
139
140 spi: spi {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "intel,ich9-spi";
Bin Meng93ea4ca2017-10-18 18:20:58 -0700[diff] [blame]144 intel,spi-lock-down;
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]145
146 spi-flash@0 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0>;
Neil Armstrongf6625b42019-02-10 10:16:21 +0000[diff] [blame^]150 compatible = "macronix,mx25u6435f", "jedec,spi-nor";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]151 memory-map = <0xff800000 0x00800000>;
152 rw-mrc-cache {
153 label = "rw-mrc-cache";
154 reg = <0x005e0000 0x00010000>;
155 };
156 };
157 };
158 };
159 };
160
161 fsp {
162 compatible = "intel,braswell-fsp";
163 fsp,memory-upd {
164 compatible = "intel,braswell-fsp-memory";
165 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
166 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
167 fsp,mrc-init-spd-addr1 = <0xa0>;
168 fsp,mrc-init-spd-addr2 = <0xa2>;
169 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
170 fsp,aperture-size = <APERTURE_SIZE_256MB>;
171 fsp,gtt-size = <GTT_SIZE_1MB>;
172 fsp,enable-dvfs;
173 fsp,memory-type = <DRAM_TYPE_DDR3>;
174 };
175 fsp,silicon-upd {
176 compatible = "intel,braswell-fsp-silicon";
177 fsp,sdcard-mode = <SDCARD_MODE_PCI>;
178 fsp,enable-hsuart1;
179 fsp,enable-sata;
180 fsp,enable-xhci;
181 fsp,lpe-mode = <LPE_MODE_PCI>;
182 fsp,enable-dma0;
183 fsp,enable-dma1;
184 fsp,enable-i2c0;
185 fsp,enable-i2c1;
186 fsp,enable-i2c2;
187 fsp,enable-i2c3;
188 fsp,enable-i2c4;
189 fsp,enable-i2c5;
190 fsp,enable-i2c6;
191 fsp,emmc-mode = <EMMC_MODE_PCI>;
192 fsp,sata-speed = <SATA_SPEED_GEN3>;
193 fsp,pmic-i2c-bus = <0>;
194 fsp,enable-isp;
195 fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]196 fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
197 fsp,sd-detect-chk;
198 };
199 };
200
201 microcode {
202 update@0 {
203#include "microcode/m01406c2220.dtsi"
204 };
205 update@1 {
206#include "microcode/m01406c3363.dtsi"
207 };
208 update@2 {
209#include "microcode/m01406c440a.dtsi"
210 };
211 };
212
213};