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git01.mediatek.com / filogic / uboot / 2bc8ecd0c581e3d4bbec93f1b3cd6afc1037763e / . / arch / x86 / dts / cherryhill.dts
blob: 840a6699568f9459900d7d7d6de0763d47e34727 [file] [log] [blame]
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]1/*
2 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/dts-v1/;
8
9#include <asm/arch-braswell/fsp/fsp_configs.h>
10#include <dt-bindings/interrupt-router/intel-irq.h>
11
12/include/ "skeleton.dtsi"
13/include/ "serial.dtsi"
14/include/ "rtc.dtsi"
15/include/ "tsc_timer.dtsi"
16
17/ {
18 model = "Intel Cherry Hill";
19 compatible = "intel,cherryhill", "intel,braswell";
20
21 aliases {
22 serial0 = &serial;
23 spi0 = &spi;
24 };
25
26 config {
27 silent_console = <0>;
28 };
29
30 chosen {
31 stdout-path = "/serial";
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 cpu@0 {
39 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame^]40 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]41 reg = <0>;
42 intel,apic-id = <0>;
43 };
44
45 cpu@1 {
46 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame^]47 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]48 reg = <1>;
49 intel,apic-id = <2>;
50 };
51
52 cpu@2 {
53 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame^]54 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]55 reg = <2>;
56 intel,apic-id = <4>;
57 };
58
59 cpu@3 {
60 device_type = "cpu";
Bin Meng2bc8ecd2017-10-18 18:20:53 -0700[diff] [blame^]61 compatible = "cpu-x86";
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]62 reg = <3>;
63 intel,apic-id = <6>;
64 };
65 };
66
67 pci {
68 compatible = "pci-x86";
69 #address-cells = <3>;
70 #size-cells = <2>;
71 u-boot,dm-pre-reloc;
72 ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
73 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
74 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
75
76 pch@1f,0 {
77 reg = <0x0000f800 0 0 0 0>;
78 compatible = "intel,pch9";
79 #address-cells = <1>;
80 #size-cells = <1>;
81
82 irq-router {
83 compatible = "intel,irq-router";
84 intel,pirq-config = "ibase";
85 intel,ibase-offset = <0x50>;
86 intel,pirq-link = <8 8>;
87 intel,pirq-mask = <0xdee0>;
88 intel,pirq-routing = <
89 /* Braswell PCI devices */
90 PCI_BDF(0, 2, 0) INTA PIRQA
91 PCI_BDF(0, 3, 0) INTA PIRQA
92 PCI_BDF(0, 11, 0) INTA PIRQA
93 PCI_BDF(0, 16, 0) INTA PIRQA
94 PCI_BDF(0, 17, 0) INTA PIRQA
95 PCI_BDF(0, 18, 0) INTA PIRQA
96 PCI_BDF(0, 19, 0) INTA PIRQA
97 PCI_BDF(0, 20, 0) INTA PIRQA
98 PCI_BDF(0, 21, 0) INTA PIRQA
99 PCI_BDF(0, 24, 0) INTA PIRQA
100 PCI_BDF(0, 24, 1) INTC PIRQC
101 PCI_BDF(0, 24, 2) INTD PIRQD
102 PCI_BDF(0, 24, 3) INTB PIRQB
103 PCI_BDF(0, 24, 4) INTA PIRQA
104 PCI_BDF(0, 24, 5) INTC PIRQC
105 PCI_BDF(0, 24, 6) INTD PIRQD
106 PCI_BDF(0, 24, 7) INTB PIRQB
107 PCI_BDF(0, 26, 0) INTA PIRQA
108 PCI_BDF(0, 27, 0) INTA PIRQA
109 PCI_BDF(0, 28, 0) INTA PIRQA
110 PCI_BDF(0, 28, 1) INTB PIRQB
111 PCI_BDF(0, 28, 2) INTC PIRQC
112 PCI_BDF(0, 28, 3) INTD PIRQD
113 PCI_BDF(0, 30, 0) INTA PIRQA
114 PCI_BDF(0, 30, 3) INTA PIRQA
115 PCI_BDF(0, 30, 4) INTA PIRQA
116 PCI_BDF(0, 31, 0) INTB PIRQB
117 PCI_BDF(0, 31, 3) INTB PIRQB
118
119 /*
120 * PCIe root ports downstream
121 * interrupts
122 */
123 PCI_BDF(1, 0, 0) INTA PIRQA
124 PCI_BDF(1, 0, 0) INTB PIRQB
125 PCI_BDF(1, 0, 0) INTC PIRQC
126 PCI_BDF(1, 0, 0) INTD PIRQD
127 PCI_BDF(2, 0, 0) INTA PIRQB
128 PCI_BDF(2, 0, 0) INTB PIRQC
129 PCI_BDF(2, 0, 0) INTC PIRQD
130 PCI_BDF(2, 0, 0) INTD PIRQA
131 PCI_BDF(3, 0, 0) INTA PIRQC
132 PCI_BDF(3, 0, 0) INTB PIRQD
133 PCI_BDF(3, 0, 0) INTC PIRQA
134 PCI_BDF(3, 0, 0) INTD PIRQB
135 PCI_BDF(4, 0, 0) INTA PIRQD
136 PCI_BDF(4, 0, 0) INTB PIRQA
137 PCI_BDF(4, 0, 0) INTC PIRQB
138 PCI_BDF(4, 0, 0) INTD PIRQC
139 >;
140 };
141
142 spi: spi {
143 #address-cells = <1>;
144 #size-cells = <0>;
145 compatible = "intel,ich9-spi";
146
147 spi-flash@0 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <0>;
151 compatible = "macronix,mx25u6435f", "spi-flash";
152 memory-map = <0xff800000 0x00800000>;
153 rw-mrc-cache {
154 label = "rw-mrc-cache";
155 reg = <0x005e0000 0x00010000>;
156 };
157 };
158 };
159 };
160 };
161
162 fsp {
163 compatible = "intel,braswell-fsp";
164 fsp,memory-upd {
165 compatible = "intel,braswell-fsp-memory";
166 fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;
167 fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
168 fsp,mrc-init-spd-addr1 = <0xa0>;
169 fsp,mrc-init-spd-addr2 = <0xa2>;
170 fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;
171 fsp,aperture-size = <APERTURE_SIZE_256MB>;
172 fsp,gtt-size = <GTT_SIZE_1MB>;
173 fsp,enable-dvfs;
174 fsp,memory-type = <DRAM_TYPE_DDR3>;
175 };
176 fsp,silicon-upd {
177 compatible = "intel,braswell-fsp-silicon";
178 fsp,sdcard-mode = <SDCARD_MODE_PCI>;
179 fsp,enable-hsuart1;
180 fsp,enable-sata;
181 fsp,enable-xhci;
182 fsp,lpe-mode = <LPE_MODE_PCI>;
183 fsp,enable-dma0;
184 fsp,enable-dma1;
185 fsp,enable-i2c0;
186 fsp,enable-i2c1;
187 fsp,enable-i2c2;
188 fsp,enable-i2c3;
189 fsp,enable-i2c4;
190 fsp,enable-i2c5;
191 fsp,enable-i2c6;
192 fsp,emmc-mode = <EMMC_MODE_PCI>;
193 fsp,sata-speed = <SATA_SPEED_GEN3>;
194 fsp,pmic-i2c-bus = <0>;
195 fsp,enable-isp;
196 fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;
Bin Meng4ba75702017-08-15 22:42:02 -0700[diff] [blame]197 fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;
198 fsp,sd-detect-chk;
199 };
200 };
201
202 microcode {
203 update@0 {
204#include "microcode/m01406c2220.dtsi"
205 };
206 update@1 {
207#include "microcode/m01406c3363.dtsi"
208 };
209 update@2 {
210#include "microcode/m01406c440a.dtsi"
211 };
212 };
213
214};