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git01.mediatek.com / filogic / uboot / f58d83cdb193d7634b17c3cee3679d581066b42f / . / drivers / net / fm / ls1043.c
blob: ba4da69423aa29db85123a9c0319dc816f6e759e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]2/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]4 */
5#include <common.h>
6#include <phy.h>
7#include <fm_eth.h>
8#include <asm/io.h>
9#include <asm/arch/fsl_serdes.h>
10
11#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
12#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
13#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
14#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
15#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
16#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
17#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
18#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
19#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
20
21u32 port_to_devdisr[] = {
22 [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
23 [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
24 [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
25 [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
26 [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
27 [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
28 [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
29 [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
30 [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
31 [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
32 [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
33 [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
34};
35
36static int is_device_disabled(enum fm_port port)
37{
38 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
39 u32 devdisr2 = in_be32(&gur->devdisr2);
40
41 return port_to_devdisr[port] & devdisr2;
42}
43
44void fman_disable_port(enum fm_port port)
45{
46 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
47
48 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
49}
50
51phy_interface_t fman_port_enet_if(enum fm_port port)
52{
53 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
54 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
55
Mingkai Hu8ce45872015-12-07 16:58:52 +0800[diff] [blame]56 if (is_device_disabled(port))
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]57 return PHY_INTERFACE_MODE_NONE;
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]58
59 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
60 return PHY_INTERFACE_MODE_XGMII;
61
62 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
63 return PHY_INTERFACE_MODE_NONE;
64
65 if (port == FM1_DTSEC3)
66 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
67 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
Madalin Bucur7c955cc2020-03-12 14:53:45 +0200[diff] [blame]68 return PHY_INTERFACE_MODE_RGMII_ID;
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]69 }
70 if (port == FM1_DTSEC4)
71 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
72 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
Madalin Bucur7c955cc2020-03-12 14:53:45 +0200[diff] [blame]73 return PHY_INTERFACE_MODE_RGMII_ID;
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame]74 }
75
76 /* handle SGMII */
77 switch (port) {
78 case FM1_DTSEC1:
79 case FM1_DTSEC2:
80 if ((port == FM1_DTSEC2) &&
81 is_serdes_configured(SGMII_2500_FM1_DTSEC2))
82 return PHY_INTERFACE_MODE_SGMII_2500;
83 case FM1_DTSEC5:
84 case FM1_DTSEC6:
85 case FM1_DTSEC9:
86 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
87 return PHY_INTERFACE_MODE_SGMII;
88 else if ((port == FM1_DTSEC9) &&
89 is_serdes_configured(SGMII_2500_FM1_DTSEC9))
90 return PHY_INTERFACE_MODE_SGMII_2500;
91 break;
92 default:
93 break;
94 }
95
96 /* handle QSGMII */
97 switch (port) {
98 case FM1_DTSEC1:
99 case FM1_DTSEC2:
100 case FM1_DTSEC5:
101 case FM1_DTSEC6:
102 /* only MAC 1,2,5,6 available for QSGMII */
103 if (is_serdes_configured(QSGMII_FM1_A))
104 return PHY_INTERFACE_MODE_QSGMII;
105 break;
106 default:
107 break;
108 }
109
110 return PHY_INTERFACE_MODE_NONE;
111}