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git01.mediatek.com / filogic / uboot / 046432602cd91817986868cb54d862f2f71d3cf1 / . / drivers / net / fm / ls1043.c
blob: cf2cc95a3a4c80196043ca3571f8a9897ca1e2cb [file] [log] [blame]
Shaohui Xie04643262015-10-26 19:47:54 +0800[diff] [blame^]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <phy.h>
8#include <fm_eth.h>
9#include <asm/io.h>
10#include <asm/arch/fsl_serdes.h>
11
12#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */
13#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
14#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000
15#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000
16#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */
17#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
18#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000
19#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000
20#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000
21
22u32 port_to_devdisr[] = {
23 [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1,
24 [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2,
25 [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3,
26 [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4,
27 [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5,
28 [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6,
29 [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9,
30 [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10,
31 [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1,
32 [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2,
33 [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3,
34 [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4,
35};
36
37static int is_device_disabled(enum fm_port port)
38{
39 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
40 u32 devdisr2 = in_be32(&gur->devdisr2);
41
42 return port_to_devdisr[port] & devdisr2;
43}
44
45void fman_disable_port(enum fm_port port)
46{
47 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
48
49 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
50}
51
52phy_interface_t fman_port_enet_if(enum fm_port port)
53{
54 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
55 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
56
57 if (is_device_disabled(port)) {
58 printf("%s:%d: port(%d) is disabled\n", __func__,
59 __LINE__, port);
60 return PHY_INTERFACE_MODE_NONE;
61 }
62
63 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
64 return PHY_INTERFACE_MODE_XGMII;
65
66 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
67 return PHY_INTERFACE_MODE_NONE;
68
69 if (port == FM1_DTSEC3)
70 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
71 FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
72 printf("%s:%d: port(FM1_DTSEC3) is OK\n",
73 __func__, __LINE__);
74 return PHY_INTERFACE_MODE_RGMII;
75 }
76 if (port == FM1_DTSEC4)
77 if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
78 FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
79 printf("%s:%d: port(FM1_DTSEC4) is OK\n",
80 __func__, __LINE__);
81 return PHY_INTERFACE_MODE_RGMII;
82 }
83
84 /* handle SGMII */
85 switch (port) {
86 case FM1_DTSEC1:
87 case FM1_DTSEC2:
88 if ((port == FM1_DTSEC2) &&
89 is_serdes_configured(SGMII_2500_FM1_DTSEC2))
90 return PHY_INTERFACE_MODE_SGMII_2500;
91 case FM1_DTSEC5:
92 case FM1_DTSEC6:
93 case FM1_DTSEC9:
94 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
95 return PHY_INTERFACE_MODE_SGMII;
96 else if ((port == FM1_DTSEC9) &&
97 is_serdes_configured(SGMII_2500_FM1_DTSEC9))
98 return PHY_INTERFACE_MODE_SGMII_2500;
99 break;
100 default:
101 break;
102 }
103
104 /* handle QSGMII */
105 switch (port) {
106 case FM1_DTSEC1:
107 case FM1_DTSEC2:
108 case FM1_DTSEC5:
109 case FM1_DTSEC6:
110 /* only MAC 1,2,5,6 available for QSGMII */
111 if (is_serdes_configured(QSGMII_FM1_A))
112 return PHY_INTERFACE_MODE_QSGMII;
113 break;
114 default:
115 break;
116 }
117
118 return PHY_INTERFACE_MODE_NONE;
119}