blob: fb410104c1fcdda5bcf0d29ea1c21c10e557ae32 [file] [log] [blame]
Yangbo Lu982f4252019-06-21 11:42:27 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Yangbo Lu023d4192021-06-03 10:51:18 +08004 * Copyright 2019, 2021 NXP
Yangbo Lu982f4252019-06-21 11:42:27 +08005 * Andy Fleming
6 * Yangbo Lu <yangbo.lu@nxp.com>
7 *
8 * Based vaguely on the pxa mmc code:
9 * (C) Copyright 2003
10 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11 */
12
13#include <config.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080014#include <command.h>
15#include <clk.h>
Simon Glass63334482019-11-14 12:57:39 -070016#include <cpu_func.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080017#include <errno.h>
18#include <hwconfig.h>
Simon Glass0f2af882020-05-10 11:40:05 -060019#include <log.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080020#include <mmc.h>
21#include <part.h>
Simon Glass274e0b02020-05-10 11:39:56 -060022#include <asm/cache.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060023#include <asm/global_data.h>
Simon Glass9bc15642020-02-03 07:36:16 -070024#include <dm/device_compat.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060025#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060026#include <linux/delay.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070027#include <linux/err.h>
Simon Glassbdd5f812023-09-14 18:21:46 -060028#include <linux/printk.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080029#include <power/regulator.h>
30#include <malloc.h>
31#include <fsl_esdhc_imx.h>
32#include <fdt_support.h>
33#include <asm/io.h>
34#include <dm.h>
35#include <asm-generic/gpio.h>
36#include <dm/pinctrl.h>
Walter Lozano8aff6732020-07-29 12:31:17 -030037#include <dt-structs.h>
38#include <mapmem.h>
39#include <dm/ofnode.h>
Haibo Chene6a999b2020-09-01 15:34:06 +080040#include <linux/iopoll.h>
Sean Anderson120fc012021-11-23 15:03:43 -050041#include <linux/dma-mapping.h>
Yangbo Lu982f4252019-06-21 11:42:27 +080042
Haibo Chene8801ac2021-02-19 11:25:32 -080043#ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
44#ifdef CONFIG_FSL_USDHC
45#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
46#endif
47#endif
48
Yangbo Lu982f4252019-06-21 11:42:27 +080049DECLARE_GLOBAL_DATA_PTR;
50
51#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
52 IRQSTATEN_CINT | \
53 IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
54 IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
55 IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
56 IRQSTATEN_DINT)
57#define MAX_TUNING_LOOP 40
Yangbo Lu982f4252019-06-21 11:42:27 +080058
59struct fsl_esdhc {
60 uint dsaddr; /* SDMA system address register */
61 uint blkattr; /* Block attributes register */
62 uint cmdarg; /* Command argument register */
63 uint xfertyp; /* Transfer type register */
64 uint cmdrsp0; /* Command response 0 register */
65 uint cmdrsp1; /* Command response 1 register */
66 uint cmdrsp2; /* Command response 2 register */
67 uint cmdrsp3; /* Command response 3 register */
68 uint datport; /* Buffer data port register */
69 uint prsstat; /* Present state register */
70 uint proctl; /* Protocol control register */
71 uint sysctl; /* System Control Register */
72 uint irqstat; /* Interrupt status register */
73 uint irqstaten; /* Interrupt status enable register */
74 uint irqsigen; /* Interrupt signal enable register */
75 uint autoc12err; /* Auto CMD error status register */
76 uint hostcapblt; /* Host controller capabilities register */
77 uint wml; /* Watermark level register */
78 uint mixctrl; /* For USDHC */
79 char reserved1[4]; /* reserved */
80 uint fevt; /* Force event register */
81 uint admaes; /* ADMA error status register */
82 uint adsaddr; /* ADMA system address register */
83 char reserved2[4];
84 uint dllctrl;
85 uint dllstat;
86 uint clktunectrlstatus;
87 char reserved3[4];
88 uint strobe_dllctrl;
89 uint strobe_dllstat;
90 char reserved4[72];
91 uint vendorspec;
92 uint mmcboot;
93 uint vendorspec2;
Giulio Benetti65b5ec12020-01-10 15:51:46 +010094 uint tuning_ctrl; /* on i.MX6/7/8/RT */
Yangbo Lu982f4252019-06-21 11:42:27 +080095 char reserved5[44];
96 uint hostver; /* Host controller version register */
97 char reserved6[4]; /* reserved */
98 uint dmaerraddr; /* DMA error address register */
99 char reserved7[4]; /* reserved */
100 uint dmaerrattr; /* DMA error attribute register */
101 char reserved8[4]; /* reserved */
102 uint hostcapblt2; /* Host controller capabilities register 2 */
103 char reserved9[8]; /* reserved */
104 uint tcr; /* Tuning control register */
105 char reserved10[28]; /* reserved */
106 uint sddirctl; /* SD direction control register */
107 char reserved11[712];/* reserved */
108 uint scr; /* eSDHC control register */
109};
110
111struct fsl_esdhc_plat {
Walter Lozano8aff6732020-07-29 12:31:17 -0300112#if CONFIG_IS_ENABLED(OF_PLATDATA)
113 /* Put this first since driver model will copy the data here */
114 struct dtd_fsl_esdhc dtplat;
115#endif
116
Yangbo Lu982f4252019-06-21 11:42:27 +0800117 struct mmc_config cfg;
118 struct mmc mmc;
119};
120
121struct esdhc_soc_data {
122 u32 flags;
Yangbo Lu982f4252019-06-21 11:42:27 +0800123};
124
125/**
126 * struct fsl_esdhc_priv
127 *
128 * @esdhc_regs: registers of the sdhc controller
129 * @sdhc_clk: Current clk of the sdhc controller
Yangbo Lu982f4252019-06-21 11:42:27 +0800130 * @cfg: mmc config
131 * @mmc: mmc
132 * Following is used when Driver Model is enabled for MMC
133 * @dev: pointer for the device
Fabio Estevam7e3d8a92020-01-06 20:11:27 -0300134 * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
Yangbo Lu982f4252019-06-21 11:42:27 +0800135 * @wp_enable: 1: enable checking wp; 0: no check
136 * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
137 * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
138 * @caps: controller capabilities
139 * @tuning_step: tuning step setting in tuning_ctrl register
140 * @start_tuning_tap: the start point for tuning in tuning_ctrl register
141 * @strobe_dll_delay_target: settings in strobe_dllctrl
142 * @signal_voltage: indicating the current voltage
Haibo Chen26154952021-03-22 18:55:38 +0800143 * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch
Yangbo Lu982f4252019-06-21 11:42:27 +0800144 * @cd_gpio: gpio for card detection
145 * @wp_gpio: gpio for write protection
146 */
147struct fsl_esdhc_priv {
148 struct fsl_esdhc *esdhc_regs;
149 unsigned int sdhc_clk;
150 struct clk per_clk;
Peng Fane5b6e5c2024-10-01 21:07:53 +0800151 struct clk_bulk clk_bulk;
Yangbo Lu982f4252019-06-21 11:42:27 +0800152 unsigned int clock;
153 unsigned int mode;
Sean Anderson80b81612022-01-12 08:18:52 +0900154#if !CONFIG_IS_ENABLED(DM_MMC)
Yangbo Lu982f4252019-06-21 11:42:27 +0800155 struct mmc *mmc;
156#endif
157 struct udevice *dev;
Fabio Estevam7e3d8a92020-01-06 20:11:27 -0300158 int broken_cd;
Yangbo Lu982f4252019-06-21 11:42:27 +0800159 int wp_enable;
160 int vs18_enable;
161 u32 flags;
162 u32 caps;
163 u32 tuning_step;
164 u32 tuning_start_tap;
165 u32 strobe_dll_delay_target;
166 u32 signal_voltage;
Haibo Chen26154952021-03-22 18:55:38 +0800167 u32 signal_voltage_switch_extra_delay_ms;
Yangbo Lu982f4252019-06-21 11:42:27 +0800168 struct udevice *vqmmc_dev;
169 struct udevice *vmmc_dev;
Simon Glassfa4689a2019-12-06 21:41:35 -0700170#if CONFIG_IS_ENABLED(DM_GPIO)
Yangbo Lu982f4252019-06-21 11:42:27 +0800171 struct gpio_desc cd_gpio;
172 struct gpio_desc wp_gpio;
173#endif
Sean Anderson120fc012021-11-23 15:03:43 -0500174 dma_addr_t dma_addr;
Yangbo Lu982f4252019-06-21 11:42:27 +0800175};
176
177/* Return the XFERTYP flags for a given command and data packet */
178static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
179{
180 uint xfertyp = 0;
181
182 if (data) {
183 xfertyp |= XFERTYP_DPSEL;
Sean Anderson218dfa12021-11-23 15:03:45 -0500184 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
185 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
186 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
187 xfertyp |= XFERTYP_DMAEN;
Yangbo Lu982f4252019-06-21 11:42:27 +0800188 if (data->blocks > 1) {
189 xfertyp |= XFERTYP_MSBSEL;
190 xfertyp |= XFERTYP_BCEN;
Sean Anderson218dfa12021-11-23 15:03:45 -0500191 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
192 xfertyp |= XFERTYP_AC12EN;
Yangbo Lu982f4252019-06-21 11:42:27 +0800193 }
194
195 if (data->flags & MMC_DATA_READ)
196 xfertyp |= XFERTYP_DTDSEL;
197 }
198
199 if (cmd->resp_type & MMC_RSP_CRC)
200 xfertyp |= XFERTYP_CCCEN;
201 if (cmd->resp_type & MMC_RSP_OPCODE)
202 xfertyp |= XFERTYP_CICEN;
203 if (cmd->resp_type & MMC_RSP_136)
204 xfertyp |= XFERTYP_RSPTYP_136;
205 else if (cmd->resp_type & MMC_RSP_BUSY)
206 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
207 else if (cmd->resp_type & MMC_RSP_PRESENT)
208 xfertyp |= XFERTYP_RSPTYP_48;
209
210 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
211 xfertyp |= XFERTYP_CMDTYP_ABORT;
212
213 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
214}
215
Yangbo Lu982f4252019-06-21 11:42:27 +0800216/*
217 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
218 */
219static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
220 struct mmc_data *data)
221{
222 struct fsl_esdhc *regs = priv->esdhc_regs;
223 uint blocks;
224 char *buffer;
225 uint databuf;
226 uint size;
227 uint irqstat;
228 ulong start;
229
230 if (data->flags & MMC_DATA_READ) {
231 blocks = data->blocks;
232 buffer = data->dest;
233 while (blocks) {
234 start = get_timer(0);
235 size = data->blocksize;
236 irqstat = esdhc_read32(&regs->irqstat);
237 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
238 if (get_timer(start) > PIO_TIMEOUT) {
239 printf("\nData Read Failed in PIO Mode.");
240 return;
241 }
242 }
243 while (size && (!(irqstat & IRQSTAT_TC))) {
244 udelay(100); /* Wait before last byte transfer complete */
245 irqstat = esdhc_read32(&regs->irqstat);
246 databuf = in_le32(&regs->datport);
247 *((uint *)buffer) = databuf;
248 buffer += 4;
249 size -= 4;
250 }
251 blocks--;
252 }
253 } else {
254 blocks = data->blocks;
255 buffer = (char *)data->src;
256 while (blocks) {
257 start = get_timer(0);
258 size = data->blocksize;
259 irqstat = esdhc_read32(&regs->irqstat);
260 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
261 if (get_timer(start) > PIO_TIMEOUT) {
262 printf("\nData Write Failed in PIO Mode.");
263 return;
264 }
265 }
266 while (size && (!(irqstat & IRQSTAT_TC))) {
267 udelay(100); /* Wait before last byte transfer complete */
268 databuf = *((uint *)buffer);
269 buffer += 4;
270 size -= 4;
271 irqstat = esdhc_read32(&regs->irqstat);
272 out_le32(&regs->datport, databuf);
273 }
274 blocks--;
275 }
276 }
277}
Yangbo Lu982f4252019-06-21 11:42:27 +0800278
Sean Andersonaa6d91d2021-11-23 15:03:44 -0500279static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
280 struct mmc_data *data)
Yangbo Lu982f4252019-06-21 11:42:27 +0800281{
Yangbo Lu982f4252019-06-21 11:42:27 +0800282 struct fsl_esdhc *regs = priv->esdhc_regs;
Sean Andersonaa6d91d2021-11-23 15:03:44 -0500283 uint wml_value = data->blocksize / 4;
Yangbo Lu982f4252019-06-21 11:42:27 +0800284
285 if (data->flags & MMC_DATA_READ) {
286 if (wml_value > WML_RD_WML_MAX)
287 wml_value = WML_RD_WML_MAX_VAL;
288
289 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Yangbo Lu982f4252019-06-21 11:42:27 +0800290 } else {
Yangbo Lu982f4252019-06-21 11:42:27 +0800291 if (wml_value > WML_WR_WML_MAX)
292 wml_value = WML_WR_WML_MAX_VAL;
Sean Andersonaa6d91d2021-11-23 15:03:44 -0500293
294 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
295 wml_value << 16);
296 }
297}
Sean Andersonaa6d91d2021-11-23 15:03:44 -0500298
299static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
300{
301 uint trans_bytes = data->blocksize * data->blocks;
302 struct fsl_esdhc *regs = priv->esdhc_regs;
303 void *buf;
304
305 if (data->flags & MMC_DATA_WRITE)
306 buf = (void *)data->src;
307 else
308 buf = data->dest;
309
310 priv->dma_addr = dma_map_single(buf, trans_bytes,
311 mmc_get_dma_dir(data));
312 if (upper_32_bits(priv->dma_addr))
313 printf("Cannot use 64 bit addresses with SDMA\n");
314 esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
315 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
316}
317
318static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
319 struct mmc_data *data)
320{
321 int timeout;
322 bool is_write = data->flags & MMC_DATA_WRITE;
323 struct fsl_esdhc *regs = priv->esdhc_regs;
324
325 if (is_write) {
326 if (priv->wp_enable && !(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
327 printf("Cannot write to locked SD card.\n");
328 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +0800329 } else {
Simon Glassfa4689a2019-12-06 21:41:35 -0700330#if CONFIG_IS_ENABLED(DM_GPIO)
331 if (dm_gpio_is_valid(&priv->wp_gpio) &&
332 dm_gpio_get_value(&priv->wp_gpio)) {
Sean Andersonaa6d91d2021-11-23 15:03:44 -0500333 printf("Cannot write to locked SD card.\n");
334 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +0800335 }
336#endif
337 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800338 }
339
Marcel Ziswiler86376fd2022-01-31 23:08:31 +0100340 esdhc_setup_watermark_level(priv, data);
341 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
Sean Anderson218dfa12021-11-23 15:03:45 -0500342 esdhc_setup_dma(priv, data);
Yangbo Lu982f4252019-06-21 11:42:27 +0800343
344 /* Calculate the timeout period for data transactions */
345 /*
346 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
347 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
348 * So, Number of SD Clock cycles for 0.25sec should be minimum
349 * (SD Clock/sec * 0.25 sec) SD Clock cycles
350 * = (mmc->clock * 1/4) SD Clock cycles
351 * As 1) >= 2)
352 * => (2^(timeout+13)) >= mmc->clock * 1/4
353 * Taking log2 both the sides
354 * => timeout + 13 >= log2(mmc->clock/4)
355 * Rounding up to next power of 2
356 * => timeout + 13 = log2(mmc->clock/4) + 1
357 * => timeout + 13 = fls(mmc->clock/4)
358 *
359 * However, the MMC spec "It is strongly recommended for hosts to
360 * implement more than 500ms timeout value even if the card
361 * indicates the 250ms maximum busy length." Even the previous
362 * value of 300ms is known to be insufficient for some cards.
363 * So, we use
364 * => timeout + 13 = fls(mmc->clock/2)
365 */
366 timeout = fls(mmc->clock/2);
367 timeout -= 13;
368
369 if (timeout > 14)
370 timeout = 14;
371
372 if (timeout < 0)
373 timeout = 0;
374
Sean Anderson218dfa12021-11-23 15:03:45 -0500375 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
376 (timeout == 4 || timeout == 8 || timeout == 12))
Yangbo Lu982f4252019-06-21 11:42:27 +0800377 timeout++;
Yangbo Lu982f4252019-06-21 11:42:27 +0800378
Sean Anderson218dfa12021-11-23 15:03:45 -0500379 if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
380 timeout = 0xE;
381
Yangbo Lu982f4252019-06-21 11:42:27 +0800382 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
383
384 return 0;
385}
386
Sean Anderson3e330792021-11-23 15:03:46 -0500387#if IS_ENABLED(CONFIG_MCF5441x)
Yangbo Lu982f4252019-06-21 11:42:27 +0800388/*
389 * Swaps 32-bit words to little-endian byte order.
390 */
391static inline void sd_swap_dma_buff(struct mmc_data *data)
392{
393 int i, size = data->blocksize >> 2;
394 u32 *buffer = (u32 *)data->dest;
395 u32 sw;
396
397 while (data->blocks--) {
398 for (i = 0; i < size; i++) {
399 sw = __sw32(*buffer);
400 *buffer++ = sw;
401 }
402 }
403}
Sean Anderson218dfa12021-11-23 15:03:45 -0500404#else
405static inline void sd_swap_dma_buff(struct mmc_data *data)
406{
407 return;
408}
Yangbo Lu982f4252019-06-21 11:42:27 +0800409#endif
410
411/*
412 * Sends a command out on the bus. Takes the mmc pointer,
413 * a command pointer, and an optional data pointer.
414 */
415static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
416 struct mmc_cmd *cmd, struct mmc_data *data)
417{
418 int err = 0;
419 uint xfertyp;
420 uint irqstat;
421 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
422 struct fsl_esdhc *regs = priv->esdhc_regs;
423 unsigned long start;
424
Sean Anderson218dfa12021-11-23 15:03:45 -0500425 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
426 cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
Yangbo Lu982f4252019-06-21 11:42:27 +0800427 return 0;
Yangbo Lu982f4252019-06-21 11:42:27 +0800428
429 esdhc_write32(&regs->irqstat, -1);
430
431 sync();
432
433 /* Wait for the bus to be idle */
434 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
435 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
436 ;
437
438 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
439 ;
440
Yangbo Lu982f4252019-06-21 11:42:27 +0800441 /* Set up for a data transfer if we have one */
442 if (data) {
443 err = esdhc_setup_data(priv, mmc, data);
444 if(err)
445 return err;
Yangbo Lu982f4252019-06-21 11:42:27 +0800446 }
447
448 /* Figure out the transfer arguments */
449 xfertyp = esdhc_xfertyp(cmd, data);
450
451 /* Mask all irqs */
452 esdhc_write32(&regs->irqsigen, 0);
453
454 /* Send the command */
455 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
Simon Glass87f79c52022-01-22 05:07:24 -0700456 if (IS_ENABLED(CONFIG_FSL_USDHC)) {
Sean Anderson3e330792021-11-23 15:03:46 -0500457 u32 mixctrl = esdhc_read32(&regs->mixctrl);
458
459 esdhc_write32(&regs->mixctrl,
460 (mixctrl & 0xFFFFFF80) | (xfertyp & 0x7F)
461 | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
462 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
463 } else {
464 esdhc_write32(&regs->xfertyp, xfertyp);
465 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800466
467 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
468 (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
469 flags = IRQSTAT_BRR;
470
471 /* Wait for the command to complete */
472 start = get_timer(0);
473 while (!(esdhc_read32(&regs->irqstat) & flags)) {
474 if (get_timer(start) > 1000) {
475 err = -ETIMEDOUT;
476 goto out;
477 }
478 }
479
480 irqstat = esdhc_read32(&regs->irqstat);
481
482 if (irqstat & CMD_ERR) {
483 err = -ECOMM;
484 goto out;
485 }
486
487 if (irqstat & IRQSTAT_CTOE) {
488 err = -ETIMEDOUT;
489 goto out;
490 }
491
Yangbo Lu982f4252019-06-21 11:42:27 +0800492 /* Workaround for ESDHC errata ENGcm03648 */
493 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Peng Fan3dbea592019-07-10 09:35:30 +0000494 int timeout = 50000;
Yangbo Lu982f4252019-06-21 11:42:27 +0800495
Peng Fan3dbea592019-07-10 09:35:30 +0000496 /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
Yangbo Lu982f4252019-06-21 11:42:27 +0800497 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
498 PRSSTAT_DAT0)) {
499 udelay(100);
500 timeout--;
501 }
502
503 if (timeout <= 0) {
504 printf("Timeout waiting for DAT0 to go high!\n");
505 err = -ETIMEDOUT;
506 goto out;
507 }
508 }
509
510 /* Copy the response to the response buffer */
511 if (cmd->resp_type & MMC_RSP_136) {
512 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
513
514 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
515 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
516 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
517 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
518 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
519 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
520 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
521 cmd->response[3] = (cmdrsp0 << 8);
522 } else
523 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
524
525 /* Wait until all of the blocks are transferred */
526 if (data) {
Sean Anderson218dfa12021-11-23 15:03:45 -0500527 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
528 esdhc_pio_read_write(priv, data);
529 } else {
530 flags = DATA_COMPLETE;
531 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
532 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
533 flags = IRQSTAT_BRR;
Yangbo Lu982f4252019-06-21 11:42:27 +0800534
Sean Anderson218dfa12021-11-23 15:03:45 -0500535 do {
536 irqstat = esdhc_read32(&regs->irqstat);
Yangbo Lu982f4252019-06-21 11:42:27 +0800537
Sean Anderson218dfa12021-11-23 15:03:45 -0500538 if (irqstat & IRQSTAT_DTOE) {
539 err = -ETIMEDOUT;
540 goto out;
541 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800542
Sean Anderson218dfa12021-11-23 15:03:45 -0500543 if (irqstat & DATA_ERR) {
544 err = -ECOMM;
545 goto out;
546 }
547 } while ((irqstat & flags) != flags);
Yangbo Lu982f4252019-06-21 11:42:27 +0800548
Sean Anderson218dfa12021-11-23 15:03:45 -0500549 /*
550 * Need invalidate the dcache here again to avoid any
551 * cache-fill during the DMA operations such as the
552 * speculative pre-fetching etc.
553 */
554 dma_unmap_single(priv->dma_addr,
555 data->blocks * data->blocksize,
556 mmc_get_dma_dir(data));
557 if (IS_ENABLED(CONFIG_MCF5441x) &&
558 (data->flags & MMC_DATA_READ))
559 sd_swap_dma_buff(data);
560 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800561 }
562
563out:
564 /* Reset CMD and DATA portions on error */
565 if (err) {
566 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
567 SYSCTL_RSTC);
568 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
569 ;
570
571 if (data) {
572 esdhc_write32(&regs->sysctl,
573 esdhc_read32(&regs->sysctl) |
574 SYSCTL_RSTD);
575 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
576 ;
577 }
578
579 /* If this was CMD11, then notify that power cycle is needed */
580 if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
581 printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
582 }
583
584 esdhc_write32(&regs->irqstat, -1);
585
586 return err;
587}
588
589static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
590{
591 struct fsl_esdhc *regs = priv->esdhc_regs;
592 int div = 1;
Haibo Chene6a999b2020-09-01 15:34:06 +0800593 u32 tmp;
Sean Anderson218dfa12021-11-23 15:03:45 -0500594 int ret, pre_div;
Yangbo Lu982f4252019-06-21 11:42:27 +0800595 int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
596 int sdhc_clk = priv->sdhc_clk;
597 uint clk;
598
Sean Anderson3e330792021-11-23 15:03:46 -0500599#if IS_ENABLED(CONFIG_MX53)
Haibo Chen84516a72022-02-11 19:16:56 +0800600 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
601 pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
Sean Anderson218dfa12021-11-23 15:03:45 -0500602#else
Haibo Chen84516a72022-02-11 19:16:56 +0800603 pre_div = 1;
Sean Anderson218dfa12021-11-23 15:03:45 -0500604#endif
Sean Anderson218dfa12021-11-23 15:03:45 -0500605
Yangbo Lu982f4252019-06-21 11:42:27 +0800606 while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
607 pre_div *= 2;
608
609 while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
610 div++;
611
Haibo Chen8be0ba32022-02-11 19:16:57 +0800612 mmc->clock = sdhc_clk / pre_div / div / ddr_pre_div;
613
Yangbo Lu982f4252019-06-21 11:42:27 +0800614 pre_div >>= 1;
615 div -= 1;
616
617 clk = (pre_div << 8) | (div << 4);
618
Sean Anderson218dfa12021-11-23 15:03:45 -0500619 if (IS_ENABLED(CONFIG_FSL_USDHC))
620 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
621 else
622 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Yangbo Lu982f4252019-06-21 11:42:27 +0800623
624 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
625
Haibo Chene6a999b2020-09-01 15:34:06 +0800626 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
627 if (ret)
628 pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
Yangbo Lu982f4252019-06-21 11:42:27 +0800629
Sean Anderson218dfa12021-11-23 15:03:45 -0500630 if (IS_ENABLED(CONFIG_FSL_USDHC))
631 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
632 else
633 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
Yangbo Lu982f4252019-06-21 11:42:27 +0800634
635 priv->clock = clock;
636}
637
Tom Rinidec7ea02024-05-20 13:35:03 -0600638#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Yangbo Lu982f4252019-06-21 11:42:27 +0800639static int esdhc_change_pinstate(struct udevice *dev)
640{
641 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
642 int ret;
643
644 switch (priv->mode) {
645 case UHS_SDR50:
646 case UHS_DDR50:
647 ret = pinctrl_select_state(dev, "state_100mhz");
648 break;
649 case UHS_SDR104:
650 case MMC_HS_200:
651 case MMC_HS_400:
Peng Fan69b9d3a2019-07-10 09:35:26 +0000652 case MMC_HS_400_ES:
Yangbo Lu982f4252019-06-21 11:42:27 +0800653 ret = pinctrl_select_state(dev, "state_200mhz");
654 break;
655 default:
656 ret = pinctrl_select_state(dev, "default");
657 break;
658 }
659
660 if (ret)
661 printf("%s %d error\n", __func__, priv->mode);
662
663 return ret;
664}
665
666static void esdhc_reset_tuning(struct mmc *mmc)
667{
668 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
669 struct fsl_esdhc *regs = priv->esdhc_regs;
670
671 if (priv->flags & ESDHC_FLAG_USDHC) {
672 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
673 esdhc_clrbits32(&regs->autoc12err,
674 MIX_CTRL_SMPCLK_SEL |
675 MIX_CTRL_EXE_TUNE);
676 }
677 }
678}
679
680static void esdhc_set_strobe_dll(struct mmc *mmc)
681{
682 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
683 struct fsl_esdhc *regs = priv->esdhc_regs;
684 u32 val;
685
686 if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
Haibo Chen920f5d02020-09-30 15:52:23 +0800687 esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
Oleksandr Suvorovd4245c22021-09-08 21:56:43 +0300688 /* clear the reset bit on strobe dll before any setting */
689 esdhc_write32(&regs->strobe_dllctrl, 0);
Yangbo Lu982f4252019-06-21 11:42:27 +0800690
691 /*
692 * enable strobe dll ctrl and adjust the delay target
693 * for the uSDHC loopback read clock
694 */
695 val = ESDHC_STROBE_DLL_CTRL_ENABLE |
Oleksandr Suvorovd4245c22021-09-08 21:56:43 +0300696 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
Yangbo Lu982f4252019-06-21 11:42:27 +0800697 (priv->strobe_dll_delay_target <<
698 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
Haibo Chen920f5d02020-09-30 15:52:23 +0800699 esdhc_write32(&regs->strobe_dllctrl, val);
Oleksandr Suvorovd4245c22021-09-08 21:56:43 +0300700 /* wait 5us to make sure strobe dll status register stable */
701 mdelay(5);
Haibo Chen920f5d02020-09-30 15:52:23 +0800702 val = esdhc_read32(&regs->strobe_dllstat);
Yangbo Lu982f4252019-06-21 11:42:27 +0800703 if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
704 pr_warn("HS400 strobe DLL status REF not lock!\n");
705 if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
706 pr_warn("HS400 strobe DLL status SLV not lock!\n");
707 }
708}
709
710static int esdhc_set_timing(struct mmc *mmc)
711{
712 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
713 struct fsl_esdhc *regs = priv->esdhc_regs;
714 u32 mixctrl;
715
Haibo Chen920f5d02020-09-30 15:52:23 +0800716 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800717 mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
718
719 switch (mmc->selected_mode) {
720 case MMC_LEGACY:
Yangbo Lu982f4252019-06-21 11:42:27 +0800721 esdhc_reset_tuning(mmc);
Haibo Chen920f5d02020-09-30 15:52:23 +0800722 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800723 break;
724 case MMC_HS_400:
Peng Fan69b9d3a2019-07-10 09:35:26 +0000725 case MMC_HS_400_ES:
Yangbo Lu982f4252019-06-21 11:42:27 +0800726 mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
Haibo Chen920f5d02020-09-30 15:52:23 +0800727 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800728 break;
729 case MMC_HS:
730 case MMC_HS_52:
731 case MMC_HS_200:
732 case SD_HS:
733 case UHS_SDR12:
734 case UHS_SDR25:
735 case UHS_SDR50:
736 case UHS_SDR104:
Haibo Chen920f5d02020-09-30 15:52:23 +0800737 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800738 break;
739 case UHS_DDR50:
740 case MMC_DDR_52:
741 mixctrl |= MIX_CTRL_DDREN;
Haibo Chen920f5d02020-09-30 15:52:23 +0800742 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800743 break;
744 default:
745 printf("Not supported %d\n", mmc->selected_mode);
746 return -EINVAL;
747 }
748
749 priv->mode = mmc->selected_mode;
750
751 return esdhc_change_pinstate(mmc->dev);
752}
753
754static int esdhc_set_voltage(struct mmc *mmc)
755{
756 struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
757 struct fsl_esdhc *regs = priv->esdhc_regs;
758 int ret;
759
760 priv->signal_voltage = mmc->signal_voltage;
761 switch (mmc->signal_voltage) {
762 case MMC_SIGNAL_VOLTAGE_330:
763 if (priv->vs18_enable)
Marek Vasutba79fed2020-05-22 18:28:33 +0200764 return -ENOTSUPP;
Sean Anderson3e330792021-11-23 15:03:46 -0500765 if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
766 !IS_ERR_OR_NULL(priv->vqmmc_dev)) {
767 ret = regulator_set_value(priv->vqmmc_dev,
768 3300000);
Yangbo Lu982f4252019-06-21 11:42:27 +0800769 if (ret) {
Alexander Stein4b5cebb2024-07-05 15:27:24 +0200770 printf("Setting to 3.3V error: %d\n", ret);
Yangbo Lu982f4252019-06-21 11:42:27 +0800771 return -EIO;
772 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800773 mdelay(5);
774 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800775
776 esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
777 if (!(esdhc_read32(&regs->vendorspec) &
778 ESDHC_VENDORSPEC_VSELECT))
779 return 0;
780
781 return -EAGAIN;
782 case MMC_SIGNAL_VOLTAGE_180:
Sean Anderson3e330792021-11-23 15:03:46 -0500783 if (CONFIG_IS_ENABLED(DM_REGULATOR) &&
784 !IS_ERR_OR_NULL(priv->vqmmc_dev)) {
785 ret = regulator_set_value(priv->vqmmc_dev,
786 1800000);
Yangbo Lu982f4252019-06-21 11:42:27 +0800787 if (ret) {
Alexander Stein4b5cebb2024-07-05 15:27:24 +0200788 printf("Setting to 1.8V error: %d\n", ret);
Yangbo Lu982f4252019-06-21 11:42:27 +0800789 return -EIO;
790 }
791 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800792 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
Haibo Chen26154952021-03-22 18:55:38 +0800793 /*
794 * some board like imx8mm-evk need about 18ms to switch
795 * the IO voltage from 3.3v to 1.8v, common code only
796 * delay 10ms, so need to delay extra time to make sure
797 * the IO voltage change to 1.8v.
798 */
799 if (priv->signal_voltage_switch_extra_delay_ms)
800 mdelay(priv->signal_voltage_switch_extra_delay_ms);
Yangbo Lu982f4252019-06-21 11:42:27 +0800801 if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
802 return 0;
803
804 return -EAGAIN;
805 case MMC_SIGNAL_VOLTAGE_120:
806 return -ENOTSUPP;
807 default:
808 return 0;
809 }
810}
811
812static void esdhc_stop_tuning(struct mmc *mmc)
813{
814 struct mmc_cmd cmd;
815
816 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
817 cmd.cmdarg = 0;
818 cmd.resp_type = MMC_RSP_R1b;
819
Jaehoon Chung099814b2021-05-31 08:31:49 +0900820 mmc_send_cmd(mmc, &cmd, NULL);
Yangbo Lu982f4252019-06-21 11:42:27 +0800821}
822
823static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
824{
Simon Glassfa20e932020-12-03 16:55:20 -0700825 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +0800826 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
827 struct fsl_esdhc *regs = priv->esdhc_regs;
828 struct mmc *mmc = &plat->mmc;
Haibo Chen920f5d02020-09-30 15:52:23 +0800829 u32 irqstaten = esdhc_read32(&regs->irqstaten);
830 u32 irqsigen = esdhc_read32(&regs->irqsigen);
Haibo Chen3a385c82022-02-22 11:28:18 +0800831 int i, err, ret = -ETIMEDOUT;
832 u32 val, mixctrl, tmp;
Yangbo Lu982f4252019-06-21 11:42:27 +0800833
834 /* clock tuning is not needed for upto 52MHz */
835 if (mmc->clock <= 52000000)
836 return 0;
837
Haibo Chen3a385c82022-02-22 11:28:18 +0800838 /* make sure the card clock keep on */
839 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
840
Yangbo Lu982f4252019-06-21 11:42:27 +0800841 /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
842 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chen920f5d02020-09-30 15:52:23 +0800843 val = esdhc_read32(&regs->autoc12err);
844 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800845 val &= ~MIX_CTRL_SMPCLK_SEL;
846 mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
847
848 val |= MIX_CTRL_EXE_TUNE;
849 mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
850
Haibo Chen920f5d02020-09-30 15:52:23 +0800851 esdhc_write32(&regs->autoc12err, val);
852 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800853 }
854
855 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
Haibo Chen920f5d02020-09-30 15:52:23 +0800856 mixctrl = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800857 mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
Haibo Chen920f5d02020-09-30 15:52:23 +0800858 esdhc_write32(&regs->mixctrl, mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800859
Haibo Chen920f5d02020-09-30 15:52:23 +0800860 esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
861 esdhc_write32(&regs->irqsigen, IRQSTATEN_BRR);
Yangbo Lu982f4252019-06-21 11:42:27 +0800862
863 /*
864 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
865 * of loops reaches 40 times.
866 */
867 for (i = 0; i < MAX_TUNING_LOOP; i++) {
868 u32 ctrl;
869
870 if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
871 if (mmc->bus_width == 8)
Haibo Chen920f5d02020-09-30 15:52:23 +0800872 esdhc_write32(&regs->blkattr, 0x7080);
Yangbo Lu982f4252019-06-21 11:42:27 +0800873 else if (mmc->bus_width == 4)
Haibo Chen920f5d02020-09-30 15:52:23 +0800874 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lu982f4252019-06-21 11:42:27 +0800875 } else {
Haibo Chen920f5d02020-09-30 15:52:23 +0800876 esdhc_write32(&regs->blkattr, 0x7040);
Yangbo Lu982f4252019-06-21 11:42:27 +0800877 }
878
879 /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
Haibo Chen920f5d02020-09-30 15:52:23 +0800880 val = esdhc_read32(&regs->mixctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +0800881 val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
Haibo Chen920f5d02020-09-30 15:52:23 +0800882 esdhc_write32(&regs->mixctrl, val);
Yangbo Lu982f4252019-06-21 11:42:27 +0800883
884 /* We are using STD tuning, no need to check return value */
Marek Vasutdad81fb2024-02-20 09:36:23 +0100885 mmc_send_tuning(mmc, opcode);
Yangbo Lu982f4252019-06-21 11:42:27 +0800886
Haibo Chen920f5d02020-09-30 15:52:23 +0800887 ctrl = esdhc_read32(&regs->autoc12err);
Yangbo Lu982f4252019-06-21 11:42:27 +0800888 if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
889 (ctrl & MIX_CTRL_SMPCLK_SEL)) {
Yangbo Lu982f4252019-06-21 11:42:27 +0800890 ret = 0;
891 break;
892 }
Yangbo Lu982f4252019-06-21 11:42:27 +0800893 }
894
Haibo Chen920f5d02020-09-30 15:52:23 +0800895 esdhc_write32(&regs->irqstaten, irqstaten);
896 esdhc_write32(&regs->irqsigen, irqsigen);
Yangbo Lu982f4252019-06-21 11:42:27 +0800897
898 esdhc_stop_tuning(mmc);
899
Haibo Chen3a385c82022-02-22 11:28:18 +0800900 /* change to default setting, let host control the card clock */
901 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
902 err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
903 if (err)
904 dev_warn(dev, "card clock not gate off as expect.\n");
905
Yangbo Lu982f4252019-06-21 11:42:27 +0800906 return ret;
907}
908#endif
909
910static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
911{
912 struct fsl_esdhc *regs = priv->esdhc_regs;
913 int ret __maybe_unused;
Peng Fan2cdf52b2019-11-04 17:14:15 +0800914 u32 clock;
Yangbo Lu982f4252019-06-21 11:42:27 +0800915
Tom Rinidec7ea02024-05-20 13:35:03 -0600916#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Haibo Cheneaa2f102020-11-03 17:18:35 +0800917 /*
918 * call esdhc_set_timing() before update the clock rate,
919 * This is because current we support DDR and SDR mode,
920 * Once the DDR_EN bit is set, the card clock will be
921 * divide by 2 automatically. So need to do this before
922 * setting clock rate.
923 */
924 if (priv->mode != mmc->selected_mode) {
925 ret = esdhc_set_timing(mmc);
926 if (ret) {
927 printf("esdhc_set_timing error %d\n", ret);
928 return ret;
929 }
930 }
931#endif
932
Yangbo Lu982f4252019-06-21 11:42:27 +0800933 /* Set the clock speed */
Peng Fan2cdf52b2019-11-04 17:14:15 +0800934 clock = mmc->clock;
935 if (clock < mmc->cfg->f_min)
936 clock = mmc->cfg->f_min;
937
938 if (priv->clock != clock)
939 set_sysctl(priv, mmc, clock);
Yangbo Lu982f4252019-06-21 11:42:27 +0800940
Yangbo Lu982f4252019-06-21 11:42:27 +0800941 if (mmc->clk_disable) {
Sean Anderson3e330792021-11-23 15:03:46 -0500942 if (IS_ENABLED(CONFIG_FSL_USDHC))
943 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
944 else
945 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Yangbo Lu982f4252019-06-21 11:42:27 +0800946 } else {
Sean Anderson3e330792021-11-23 15:03:46 -0500947 if (IS_ENABLED(CONFIG_FSL_USDHC))
948 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
949 VENDORSPEC_CKEN);
950 else
951 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
Yangbo Lu982f4252019-06-21 11:42:27 +0800952 }
953
Tom Rinidec7ea02024-05-20 13:35:03 -0600954#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Haibo Cheneaa2f102020-11-03 17:18:35 +0800955 /*
956 * For HS400/HS400ES mode, make sure set the strobe dll in the
957 * target clock rate. So call esdhc_set_strobe_dll() after the
958 * clock updated.
959 */
960 if (mmc->selected_mode == MMC_HS_400 || mmc->selected_mode == MMC_HS_400_ES)
961 esdhc_set_strobe_dll(mmc);
Yangbo Lu982f4252019-06-21 11:42:27 +0800962
963 if (priv->signal_voltage != mmc->signal_voltage) {
964 ret = esdhc_set_voltage(mmc);
965 if (ret) {
Marek Vasutba79fed2020-05-22 18:28:33 +0200966 if (ret != -ENOTSUPP)
967 printf("esdhc_set_voltage error %d\n", ret);
Yangbo Lu982f4252019-06-21 11:42:27 +0800968 return ret;
969 }
970 }
971#endif
972
973 /* Set the bus width */
974 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
975
976 if (mmc->bus_width == 4)
977 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
978 else if (mmc->bus_width == 8)
979 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
980
981 return 0;
982}
983
984static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
985{
986 struct fsl_esdhc *regs = priv->esdhc_regs;
987 ulong start;
988
989 /* Reset the entire host controller */
Peng Fan97a645c2024-10-01 21:07:57 +0800990 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
Yangbo Lu982f4252019-06-21 11:42:27 +0800991
992 /* Wait until the controller is available */
993 start = get_timer(0);
Peng Fan97a645c2024-10-01 21:07:57 +0800994 while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
Yangbo Lu982f4252019-06-21 11:42:27 +0800995 if (get_timer(start) > 1000)
996 return -ETIMEDOUT;
997 }
998
Sean Anderson3e330792021-11-23 15:03:46 -0500999 if (IS_ENABLED(CONFIG_FSL_USDHC)) {
1000 /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1001 esdhc_write32(&regs->mmcboot, 0x0);
1002 /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1003 esdhc_write32(&regs->mixctrl, 0x0);
1004 esdhc_write32(&regs->clktunectrlstatus, 0x0);
Yangbo Lu982f4252019-06-21 11:42:27 +08001005
Sean Anderson3e330792021-11-23 15:03:46 -05001006 /* Put VEND_SPEC to default value */
1007 if (priv->vs18_enable)
1008 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT |
1009 ESDHC_VENDORSPEC_VSELECT);
1010 else
1011 esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
Yangbo Lu982f4252019-06-21 11:42:27 +08001012
Sean Anderson3e330792021-11-23 15:03:46 -05001013 /* Disable DLL_CTRL delay line */
1014 esdhc_write32(&regs->dllctrl, 0x0);
1015 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001016
Sean Anderson3e330792021-11-23 15:03:46 -05001017 if (IS_ENABLED(CONFIG_FSL_USDHC))
1018 esdhc_setbits32(&regs->vendorspec,
1019 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1020 else
1021 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Yangbo Lu982f4252019-06-21 11:42:27 +08001022
1023 /* Set the initial clock speed */
Sean Andersonab3d1542021-11-23 15:03:47 -05001024 set_sysctl(priv, mmc, 400000);
Yangbo Lu982f4252019-06-21 11:42:27 +08001025
1026 /* Disable the BRR and BWR bits in IRQSTAT */
1027 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1028
Yangbo Lu982f4252019-06-21 11:42:27 +08001029 /* Put the PROCTL reg back to the default */
Sean Anderson3e330792021-11-23 15:03:46 -05001030 if (IS_ENABLED(CONFIG_MCF5441x))
1031 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1032 else
1033 esdhc_write32(&regs->proctl, PROCTL_INIT);
Yangbo Lu982f4252019-06-21 11:42:27 +08001034
1035 /* Set timout to the maximum value */
1036 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1037
Ye Li56cb13e2024-10-01 21:07:54 +08001038 /* max 1ms delay with clock on for initialization */
1039 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
1040 udelay(1000);
1041 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
1042
Yangbo Lu982f4252019-06-21 11:42:27 +08001043 return 0;
1044}
1045
1046static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1047{
1048 struct fsl_esdhc *regs = priv->esdhc_regs;
1049 int timeout = 1000;
1050
Sean Anderson3e330792021-11-23 15:03:46 -05001051 if (IS_ENABLED(CONFIG_ESDHC_DETECT_QUIRK))
Yangbo Lu982f4252019-06-21 11:42:27 +08001052 return 1;
Yangbo Lu982f4252019-06-21 11:42:27 +08001053
Sean Anderson3e330792021-11-23 15:03:46 -05001054 if (CONFIG_IS_ENABLED(DM_MMC)) {
1055 if (priv->broken_cd)
1056 return 1;
Simon Glassfa4689a2019-12-06 21:41:35 -07001057#if CONFIG_IS_ENABLED(DM_GPIO)
Sean Anderson3e330792021-11-23 15:03:46 -05001058 if (dm_gpio_is_valid(&priv->cd_gpio))
1059 return dm_gpio_get_value(&priv->cd_gpio);
Yangbo Lu982f4252019-06-21 11:42:27 +08001060#endif
Sean Anderson3e330792021-11-23 15:03:46 -05001061 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001062
1063 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1064 udelay(1000);
1065
1066 return timeout > 0;
1067}
1068
Loic Poulain233c3732022-05-26 16:37:22 +02001069static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state,
1070 int timeout_us)
1071{
1072 struct fsl_esdhc *regs = priv->esdhc_regs;
1073 int ret, err;
1074 u32 tmp;
1075
1076 /* make sure the card clock keep on */
1077 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
1078
1079 ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp,
1080 !!(tmp & PRSSTAT_DAT0) == !!state,
1081 timeout_us);
1082
1083 /* change to default setting, let host control the card clock */
1084 esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
1085
1086 err = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
1087 if (err)
1088 pr_warn("card clock not gate off as expect.\n");
1089
1090 return ret;
1091}
1092
Yangbo Lu982f4252019-06-21 11:42:27 +08001093static int esdhc_reset(struct fsl_esdhc *regs)
1094{
1095 ulong start;
1096
1097 /* reset the controller */
Peng Fan97a645c2024-10-01 21:07:57 +08001098 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA | SYSCTL_RSTT);
Yangbo Lu982f4252019-06-21 11:42:27 +08001099
1100 /* hardware clears the bit when it is done */
1101 start = get_timer(0);
Peng Fan97a645c2024-10-01 21:07:57 +08001102 while ((esdhc_read32(&regs->sysctl) & (SYSCTL_RSTA | SYSCTL_RSTT))) {
Yangbo Lu982f4252019-06-21 11:42:27 +08001103 if (get_timer(start) > 100) {
1104 printf("MMC/SD: Reset never completed.\n");
1105 return -ETIMEDOUT;
1106 }
1107 }
1108
1109 return 0;
1110}
1111
1112#if !CONFIG_IS_ENABLED(DM_MMC)
1113static int esdhc_getcd(struct mmc *mmc)
1114{
1115 struct fsl_esdhc_priv *priv = mmc->priv;
1116
1117 return esdhc_getcd_common(priv);
1118}
1119
1120static int esdhc_init(struct mmc *mmc)
1121{
1122 struct fsl_esdhc_priv *priv = mmc->priv;
1123
1124 return esdhc_init_common(priv, mmc);
1125}
1126
1127static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1128 struct mmc_data *data)
1129{
1130 struct fsl_esdhc_priv *priv = mmc->priv;
1131
1132 return esdhc_send_cmd_common(priv, mmc, cmd, data);
1133}
1134
1135static int esdhc_set_ios(struct mmc *mmc)
1136{
1137 struct fsl_esdhc_priv *priv = mmc->priv;
1138
1139 return esdhc_set_ios_common(priv, mmc);
1140}
1141
Loic Poulain233c3732022-05-26 16:37:22 +02001142static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
1143{
1144 struct fsl_esdhc_priv *priv = mmc->priv;
1145
1146 return esdhc_wait_dat0_common(priv, state, timeout_us);
1147}
1148
Yangbo Lu982f4252019-06-21 11:42:27 +08001149static const struct mmc_ops esdhc_ops = {
1150 .getcd = esdhc_getcd,
1151 .init = esdhc_init,
1152 .send_cmd = esdhc_send_cmd,
1153 .set_ios = esdhc_set_ios,
Loic Poulain233c3732022-05-26 16:37:22 +02001154 .wait_dat0 = esdhc_wait_dat0,
Yangbo Lu982f4252019-06-21 11:42:27 +08001155};
1156#endif
1157
1158static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1159 struct fsl_esdhc_plat *plat)
1160{
1161 struct mmc_config *cfg;
1162 struct fsl_esdhc *regs;
Sean Anderson6dff7b72021-11-23 15:03:38 -05001163 u32 caps;
Yangbo Lu982f4252019-06-21 11:42:27 +08001164 int ret;
1165
1166 if (!priv)
1167 return -EINVAL;
1168
1169 regs = priv->esdhc_regs;
1170
1171 /* First reset the eSDHC controller */
1172 ret = esdhc_reset(regs);
1173 if (ret)
1174 return ret;
1175
Yangbo Lu982f4252019-06-21 11:42:27 +08001176 /* ColdFire, using SDHC_DATA[3] for card detection */
Sean Anderson218dfa12021-11-23 15:03:45 -05001177 if (IS_ENABLED(CONFIG_MCF5441x))
1178 esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
Yangbo Lu982f4252019-06-21 11:42:27 +08001179
Sean Anderson218dfa12021-11-23 15:03:45 -05001180 if (IS_ENABLED(CONFIG_FSL_USDHC)) {
1181 esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1182 VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1183 } else {
1184 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1185 | SYSCTL_IPGEN | SYSCTL_CKEN);
1186 /* Clearing tuning bits in case ROM has set it already */
1187 esdhc_write32(&regs->mixctrl, 0);
1188 esdhc_write32(&regs->autoc12err, 0);
1189 esdhc_write32(&regs->clktunectrlstatus, 0);
1190 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001191
1192 if (priv->vs18_enable)
1193 esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1194
Haibo Chen920f5d02020-09-30 15:52:23 +08001195 esdhc_write32(&regs->irqstaten, SDHCI_IRQ_EN_BITS);
Yangbo Lu982f4252019-06-21 11:42:27 +08001196 cfg = &plat->cfg;
Yangbo Lu982f4252019-06-21 11:42:27 +08001197
Yangbo Lu982f4252019-06-21 11:42:27 +08001198 caps = esdhc_read32(&regs->hostcapblt);
Sean Anderson218dfa12021-11-23 15:03:45 -05001199
Yangbo Lu982f4252019-06-21 11:42:27 +08001200 /*
1201 * MCF5441x RM declares in more points that sdhc clock speed must
1202 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1203 * from host capabilities.
1204 */
Sean Anderson218dfa12021-11-23 15:03:45 -05001205 if (IS_ENABLED(CONFIG_MCF5441x))
1206 caps &= ~HOSTCAPBLT_HSS;
Yangbo Lu982f4252019-06-21 11:42:27 +08001207
Sean Anderson218dfa12021-11-23 15:03:45 -05001208 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
1209 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
Sean Anderson6dff7b72021-11-23 15:03:38 -05001210
Sean Anderson218dfa12021-11-23 15:03:45 -05001211 if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
1212 caps |= HOSTCAPBLT_VS33;
Yangbo Lu982f4252019-06-21 11:42:27 +08001213
Sean Anderson6dff7b72021-11-23 15:03:38 -05001214 if (caps & HOSTCAPBLT_VS18)
1215 cfg->voltages |= MMC_VDD_165_195;
1216 if (caps & HOSTCAPBLT_VS30)
1217 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
1218 if (caps & HOSTCAPBLT_VS33)
1219 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
Yangbo Lu982f4252019-06-21 11:42:27 +08001220
1221 cfg->name = "FSL_SDHC";
Sean Anderson218dfa12021-11-23 15:03:45 -05001222
Yangbo Lu982f4252019-06-21 11:42:27 +08001223#if !CONFIG_IS_ENABLED(DM_MMC)
1224 cfg->ops = &esdhc_ops;
1225#endif
Yangbo Lu982f4252019-06-21 11:42:27 +08001226
Sean Anderson218dfa12021-11-23 15:03:45 -05001227 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE))
1228 cfg->host_caps |= MMC_MODE_DDR_52MHz;
1229
Sean Anderson6dff7b72021-11-23 15:03:38 -05001230 if (caps & HOSTCAPBLT_HSS)
Yangbo Lu982f4252019-06-21 11:42:27 +08001231 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1232
Yangbo Lu982f4252019-06-21 11:42:27 +08001233 cfg->host_caps |= priv->caps;
1234
1235 cfg->f_min = 400000;
1236 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1237
1238 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1239
Haibo Chen920f5d02020-09-30 15:52:23 +08001240 esdhc_write32(&regs->dllctrl, 0);
Yangbo Lu982f4252019-06-21 11:42:27 +08001241 if (priv->flags & ESDHC_FLAG_USDHC) {
1242 if (priv->flags & ESDHC_FLAG_STD_TUNING) {
Haibo Chen920f5d02020-09-30 15:52:23 +08001243 u32 val = esdhc_read32(&regs->tuning_ctrl);
Yangbo Lu982f4252019-06-21 11:42:27 +08001244
1245 val |= ESDHC_STD_TUNING_EN;
1246 val &= ~ESDHC_TUNING_START_TAP_MASK;
1247 val |= priv->tuning_start_tap;
1248 val &= ~ESDHC_TUNING_STEP_MASK;
1249 val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
Haibo Chen43162c32020-06-22 19:38:04 +08001250
1251 /* Disable the CMD CRC check for tuning, if not, need to
1252 * add some delay after every tuning command, because
1253 * hardware standard tuning logic will directly go to next
1254 * step once it detect the CMD CRC error, will not wait for
1255 * the card side to finally send out the tuning data, trigger
1256 * the buffer read ready interrupt immediately. If usdhc send
1257 * the next tuning command some eMMC card will stuck, can't
1258 * response, block the tuning procedure or the first command
1259 * after the whole tuning procedure always can't get any response.
1260 */
1261 val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
Haibo Chen920f5d02020-09-30 15:52:23 +08001262 esdhc_write32(&regs->tuning_ctrl, val);
Yangbo Lu982f4252019-06-21 11:42:27 +08001263 }
Adam Ford97497fd2022-01-12 07:53:56 -06001264
1265 /*
1266 * UHS doesn't have explicit ESDHC flags, so if it's
1267 * not supported, disable it in config.
1268 */
1269 if (CONFIG_IS_ENABLED(MMC_UHS_SUPPORT))
1270 cfg->host_caps |= UHS_CAPS;
Yangbo Lu982f4252019-06-21 11:42:27 +08001271
Adam Ford97497fd2022-01-12 07:53:56 -06001272 if (CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)) {
1273 if (priv->flags & ESDHC_FLAG_HS200)
1274 cfg->host_caps |= MMC_CAP(MMC_HS_200);
1275 }
1276
1277 if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)) {
1278 if (priv->flags & ESDHC_FLAG_HS400)
1279 cfg->host_caps |= MMC_CAP(MMC_HS_400);
1280 }
1281
1282 if (CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) {
1283 if (priv->flags & ESDHC_FLAG_HS400_ES)
1284 cfg->host_caps |= MMC_CAP(MMC_HS_400_ES);
1285 }
1286 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001287 return 0;
1288}
1289
1290#if !CONFIG_IS_ENABLED(DM_MMC)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001291int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
Yangbo Lu982f4252019-06-21 11:42:27 +08001292{
1293 struct fsl_esdhc_plat *plat;
1294 struct fsl_esdhc_priv *priv;
Sean Anderson1f0d6c62021-11-23 15:03:39 -05001295 struct mmc_config *mmc_cfg;
Yangbo Lu982f4252019-06-21 11:42:27 +08001296 struct mmc *mmc;
1297 int ret;
1298
1299 if (!cfg)
1300 return -EINVAL;
1301
1302 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1303 if (!priv)
1304 return -ENOMEM;
1305 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1306 if (!plat) {
1307 free(priv);
1308 return -ENOMEM;
1309 }
1310
Sean Anderson1f0d6c62021-11-23 15:03:39 -05001311 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1312 priv->sdhc_clk = cfg->sdhc_clk;
1313 priv->wp_enable = cfg->wp_enable;
1314
1315 mmc_cfg = &plat->cfg;
1316
1317 switch (cfg->max_bus_width) {
1318 case 0: /* Not set in config; assume everything is supported */
1319 case 8:
1320 mmc_cfg->host_caps |= MMC_MODE_8BIT;
1321 fallthrough;
1322 case 4:
1323 mmc_cfg->host_caps |= MMC_MODE_4BIT;
1324 fallthrough;
1325 case 1:
1326 mmc_cfg->host_caps |= MMC_MODE_1BIT;
1327 break;
1328 default:
1329 printf("invalid max bus width %u\n", cfg->max_bus_width);
Ye Lic6b90e22024-10-01 21:07:56 +08001330 free(plat);
1331 free(priv);
Sean Anderson1f0d6c62021-11-23 15:03:39 -05001332 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +08001333 }
1334
Sean Anderson218dfa12021-11-23 15:03:45 -05001335 if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
Sean Anderson1f0d6c62021-11-23 15:03:39 -05001336 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
Sean Anderson1f0d6c62021-11-23 15:03:39 -05001337
Yangbo Lu982f4252019-06-21 11:42:27 +08001338 ret = fsl_esdhc_init(priv, plat);
1339 if (ret) {
1340 debug("%s init failure\n", __func__);
1341 free(plat);
1342 free(priv);
1343 return ret;
1344 }
1345
1346 mmc = mmc_create(&plat->cfg, priv);
1347 if (!mmc)
1348 return -EIO;
1349
1350 priv->mmc = mmc;
1351
1352 return 0;
1353}
1354
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001355int fsl_esdhc_mmc_init(struct bd_info *bis)
Yangbo Lu982f4252019-06-21 11:42:27 +08001356{
1357 struct fsl_esdhc_cfg *cfg;
1358
1359 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
Tom Rini376b88a2022-10-28 20:27:13 -04001360 cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR;
Yangbo Lu982f4252019-06-21 11:42:27 +08001361 cfg->sdhc_clk = gd->arch.sdhc_clk;
1362 return fsl_esdhc_initialize(bis, cfg);
1363}
1364#endif
1365
Sean Anderson3e330792021-11-23 15:03:46 -05001366#if CONFIG_IS_ENABLED(OF_LIBFDT)
Yangbo Lu982f4252019-06-21 11:42:27 +08001367__weak int esdhc_status_fixup(void *blob, const char *compat)
1368{
Tom Rinif8967f82022-12-02 16:42:22 -05001369 if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
Yangbo Lu982f4252019-06-21 11:42:27 +08001370 do_fixup_by_compat(blob, compat, "status", "disabled",
1371 sizeof("disabled"), 1);
1372 return 1;
1373 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001374 return 0;
1375}
1376
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001377void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
Yangbo Lu982f4252019-06-21 11:42:27 +08001378{
1379 const char *compat = "fsl,esdhc";
1380
1381 if (esdhc_status_fixup(blob, compat))
1382 return;
1383
Yangbo Lu982f4252019-06-21 11:42:27 +08001384 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1385 gd->arch.sdhc_clk, 1);
Yangbo Lu982f4252019-06-21 11:42:27 +08001386}
1387#endif
1388
1389#if CONFIG_IS_ENABLED(DM_MMC)
Yangbo Lu982f4252019-06-21 11:42:27 +08001390#include <asm/arch/clock.h>
Yangbo Lu982f4252019-06-21 11:42:27 +08001391__weak void init_clk_usdhc(u32 index)
1392{
1393}
1394
Simon Glassaad29ae2020-12-03 16:55:21 -07001395static int fsl_esdhc_of_to_plat(struct udevice *dev)
Yangbo Lu982f4252019-06-21 11:42:27 +08001396{
Yangbo Lu982f4252019-06-21 11:42:27 +08001397 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001398 struct udevice *vqmmc_dev;
Walter Lozano8aff6732020-07-29 12:31:17 -03001399 int ret;
Sean Anderson3e330792021-11-23 15:03:46 -05001400
Walter Lozano8aff6732020-07-29 12:31:17 -03001401 const void *fdt = gd->fdt_blob;
1402 int node = dev_of_offset(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001403 fdt_addr_t addr;
1404 unsigned int val;
Yangbo Lu982f4252019-06-21 11:42:27 +08001405
Simon Glass6d70ba02021-08-07 07:24:06 -06001406 if (!CONFIG_IS_ENABLED(OF_REAL))
1407 return 0;
1408
Yangbo Lu982f4252019-06-21 11:42:27 +08001409 addr = dev_read_addr(dev);
1410 if (addr == FDT_ADDR_T_NONE)
1411 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +08001412 priv->esdhc_regs = (struct fsl_esdhc *)addr;
Yangbo Lu982f4252019-06-21 11:42:27 +08001413 priv->dev = dev;
1414 priv->mode = -1;
Yangbo Lu982f4252019-06-21 11:42:27 +08001415
Yangbo Lu982f4252019-06-21 11:42:27 +08001416 val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1417 priv->tuning_step = val;
1418 val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1419 ESDHC_TUNING_START_TAP_DEFAULT);
1420 priv->tuning_start_tap = val;
1421 val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1422 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1423 priv->strobe_dll_delay_target = val;
Haibo Chen26154952021-03-22 18:55:38 +08001424 val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0);
1425 priv->signal_voltage_switch_extra_delay_ms = val;
Yangbo Lu982f4252019-06-21 11:42:27 +08001426
Fabio Estevam7e3d8a92020-01-06 20:11:27 -03001427 if (dev_read_bool(dev, "broken-cd"))
1428 priv->broken_cd = 1;
1429
Yangbo Lu982f4252019-06-21 11:42:27 +08001430 if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1431 priv->wp_enable = 1;
1432 } else {
1433 priv->wp_enable = 0;
Sean Anderson5b8040b2021-11-23 15:03:40 -05001434 }
1435
Simon Glassfa4689a2019-12-06 21:41:35 -07001436#if CONFIG_IS_ENABLED(DM_GPIO)
Sean Anderson5b8040b2021-11-23 15:03:40 -05001437 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1438 GPIOD_IS_IN);
1439 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1440 GPIOD_IS_IN);
Yangbo Lu982f4252019-06-21 11:42:27 +08001441#endif
Yangbo Lu982f4252019-06-21 11:42:27 +08001442
1443 priv->vs18_enable = 0;
1444
Sean Anderson3e330792021-11-23 15:03:46 -05001445 if (!CONFIG_IS_ENABLED(DM_REGULATOR))
1446 return 0;
1447
Yangbo Lu982f4252019-06-21 11:42:27 +08001448 /*
1449 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1450 * otherwise, emmc will work abnormally.
1451 */
1452 ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1453 if (ret) {
1454 dev_dbg(dev, "no vqmmc-supply\n");
1455 } else {
Marek Vasut34e67f92020-05-22 18:19:08 +02001456 priv->vqmmc_dev = vqmmc_dev;
Yangbo Lu982f4252019-06-21 11:42:27 +08001457 ret = regulator_set_enable(vqmmc_dev, true);
1458 if (ret) {
1459 dev_err(dev, "fail to enable vqmmc-supply\n");
1460 return ret;
1461 }
1462
1463 if (regulator_get_value(vqmmc_dev) == 1800000)
1464 priv->vs18_enable = 1;
1465 }
Walter Lozano8aff6732020-07-29 12:31:17 -03001466 return 0;
1467}
1468
1469static int fsl_esdhc_probe(struct udevice *dev)
1470{
1471 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassfa20e932020-12-03 16:55:20 -07001472 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Walter Lozano8aff6732020-07-29 12:31:17 -03001473 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1474 struct esdhc_soc_data *data =
1475 (struct esdhc_soc_data *)dev_get_driver_data(dev);
1476 struct mmc *mmc;
Walter Lozano8aff6732020-07-29 12:31:17 -03001477 int ret;
1478
1479#if CONFIG_IS_ENABLED(OF_PLATDATA)
1480 struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
Walter Lozano8aff6732020-07-29 12:31:17 -03001481
1482 priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001483
1484 if (dtplat->non_removable)
Sean Anderson5b8040b2021-11-23 15:03:40 -05001485 plat->cfg.host_caps |= MMC_CAP_NONREMOVABLE;
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001486 else
Sean Anderson5b8040b2021-11-23 15:03:40 -05001487 plat->cfg.host_caps &= ~MMC_CAP_NONREMOVABLE;
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001488
Sean Anderson5b8040b2021-11-23 15:03:40 -05001489 if (CONFIG_IS_ENABLED(DM_GPIO) && !dtplat->non_removable) {
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001490 struct udevice *gpiodev;
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001491
Simon Glass0000e0d2021-03-15 17:25:28 +13001492 ret = device_get_by_ofplat_idx(dtplat->cd_gpios->idx, &gpiodev);
Walter Lozanocfc05fd2020-07-29 12:31:19 -03001493 if (ret)
1494 return ret;
1495
1496 ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
1497 dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
1498 dtplat->cd_gpios->arg[1], &priv->cd_gpio);
1499
1500 if (ret)
1501 return ret;
1502 }
Walter Lozano8aff6732020-07-29 12:31:17 -03001503#endif
1504
1505 if (data)
1506 priv->flags = data->flags;
Yangbo Lu982f4252019-06-21 11:42:27 +08001507
Yangbo Lu982f4252019-06-21 11:42:27 +08001508 /*
1509 * TODO:
1510 * Because lack of clk driver, if SDHC clk is not enabled,
1511 * need to enable it first before this driver is invoked.
1512 *
1513 * we use MXC_ESDHC_CLK to get clk freq.
1514 * If one would like to make this function work,
1515 * the aliases should be provided in dts as this:
1516 *
1517 * aliases {
1518 * mmc0 = &usdhc1;
1519 * mmc1 = &usdhc2;
1520 * mmc2 = &usdhc3;
1521 * mmc3 = &usdhc4;
1522 * };
1523 * Then if your board only supports mmc2 and mmc3, but we can
1524 * correctly get the seq as 2 and 3, then let mxc_get_clock
1525 * work as expected.
1526 */
1527
Giulio Benettidbdbc632020-01-10 15:51:45 +01001528#if CONFIG_IS_ENABLED(CLK)
1529 /* Assigned clock already set clock */
Peng Fane5b6e5c2024-10-01 21:07:53 +08001530 ret = clk_get_bulk(dev, &priv->clk_bulk);
Giulio Benettidbdbc632020-01-10 15:51:45 +01001531 if (ret) {
Peng Fane5b6e5c2024-10-01 21:07:53 +08001532 dev_err(dev, "Failed to get clks: %d\n", ret);
Giulio Benettidbdbc632020-01-10 15:51:45 +01001533 return ret;
1534 }
Peng Fane5b6e5c2024-10-01 21:07:53 +08001535
1536 ret = clk_enable_bulk(&priv->clk_bulk);
Giulio Benettidbdbc632020-01-10 15:51:45 +01001537 if (ret) {
Peng Fane5b6e5c2024-10-01 21:07:53 +08001538 dev_err(dev, "Failed to enable clks: %d\n", ret);
1539 return ret;
1540 }
1541
1542 ret = clk_get_by_name(dev, "per", &priv->per_clk);
1543 if (ret) {
1544 printf("Failed to get per_clk\n");
Giulio Benettidbdbc632020-01-10 15:51:45 +01001545 return ret;
1546 }
Yangbo Lu982f4252019-06-21 11:42:27 +08001547
Giulio Benettidbdbc632020-01-10 15:51:45 +01001548 priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1549#else
Ye Li2a4b3b92022-09-24 00:29:33 +02001550 init_clk_usdhc(dev_seq(dev));
1551
Simon Glass75e534b2020-12-16 21:20:07 -07001552 priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
Giulio Benettidbdbc632020-01-10 15:51:45 +01001553 if (priv->sdhc_clk <= 0) {
1554 dev_err(dev, "Unable to get clk for %s\n", dev->name);
1555 return -EINVAL;
Yangbo Lu982f4252019-06-21 11:42:27 +08001556 }
Giulio Benettidbdbc632020-01-10 15:51:45 +01001557#endif
Yangbo Lu982f4252019-06-21 11:42:27 +08001558
1559 ret = fsl_esdhc_init(priv, plat);
1560 if (ret) {
1561 dev_err(dev, "fsl_esdhc_init failure\n");
1562 return ret;
1563 }
1564
Simon Glass6d70ba02021-08-07 07:24:06 -06001565 if (CONFIG_IS_ENABLED(OF_REAL)) {
1566 ret = mmc_of_parse(dev, &plat->cfg);
1567 if (ret)
1568 return ret;
1569 }
Peng Fan3766a482019-07-10 09:35:24 +00001570
Yangbo Lu982f4252019-06-21 11:42:27 +08001571 mmc = &plat->mmc;
1572 mmc->cfg = &plat->cfg;
1573 mmc->dev = dev;
Yangbo Lu982f4252019-06-21 11:42:27 +08001574
1575 upriv->mmc = mmc;
1576
Ye Li56cb13e2024-10-01 21:07:54 +08001577 return 0;
Yangbo Lu982f4252019-06-21 11:42:27 +08001578}
1579
Yangbo Lu982f4252019-06-21 11:42:27 +08001580static int fsl_esdhc_get_cd(struct udevice *dev)
1581{
Sean Anderson5b8040b2021-11-23 15:03:40 -05001582 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001583 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1584
Sean Anderson5b8040b2021-11-23 15:03:40 -05001585 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
1586 return 1;
1587
Yangbo Lu982f4252019-06-21 11:42:27 +08001588 return esdhc_getcd_common(priv);
1589}
1590
1591static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1592 struct mmc_data *data)
1593{
Simon Glassfa20e932020-12-03 16:55:20 -07001594 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001595 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1596
1597 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1598}
1599
1600static int fsl_esdhc_set_ios(struct udevice *dev)
1601{
Simon Glassfa20e932020-12-03 16:55:20 -07001602 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001603 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1604
1605 return esdhc_set_ios_common(priv, &plat->mmc);
1606}
1607
Sean Anderson3e330792021-11-23 15:03:46 -05001608static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
Peng Fan69b9d3a2019-07-10 09:35:26 +00001609{
1610 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1611 struct fsl_esdhc *regs = priv->esdhc_regs;
1612 u32 m;
1613
Haibo Chen920f5d02020-09-30 15:52:23 +08001614 m = esdhc_read32(&regs->mixctrl);
Peng Fan69b9d3a2019-07-10 09:35:26 +00001615 m |= MIX_CTRL_HS400_ES;
Haibo Chen920f5d02020-09-30 15:52:23 +08001616 esdhc_write32(&regs->mixctrl, m);
Peng Fan69b9d3a2019-07-10 09:35:26 +00001617
1618 return 0;
1619}
Peng Fan69b9d3a2019-07-10 09:35:26 +00001620
Haibo Chencb78f212020-11-05 14:57:13 +08001621static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
1622 int timeout_us)
1623{
Haibo Chencb78f212020-11-05 14:57:13 +08001624 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
Haibo Chen3a385c82022-02-22 11:28:18 +08001625
Loic Poulain233c3732022-05-26 16:37:22 +02001626 return esdhc_wait_dat0_common(priv, state, timeout_us);
Haibo Chencb78f212020-11-05 14:57:13 +08001627}
1628
Ye Li56cb13e2024-10-01 21:07:54 +08001629static int fsl_esdhc_reinit(struct udevice *dev)
1630{
1631 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
1632 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1633
1634 return esdhc_init_common(priv, &plat->mmc);
1635}
1636
Yangbo Lu982f4252019-06-21 11:42:27 +08001637static const struct dm_mmc_ops fsl_esdhc_ops = {
1638 .get_cd = fsl_esdhc_get_cd,
1639 .send_cmd = fsl_esdhc_send_cmd,
1640 .set_ios = fsl_esdhc_set_ios,
Tom Rinidec7ea02024-05-20 13:35:03 -06001641#if CONFIG_IS_ENABLED(MMC_SUPPORTS_TUNING)
Yangbo Lu982f4252019-06-21 11:42:27 +08001642 .execute_tuning = fsl_esdhc_execute_tuning,
1643#endif
Peng Fan69b9d3a2019-07-10 09:35:26 +00001644#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1645 .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1646#endif
Haibo Chencb78f212020-11-05 14:57:13 +08001647 .wait_dat0 = fsl_esdhc_wait_dat0,
Ye Li56cb13e2024-10-01 21:07:54 +08001648 .reinit = fsl_esdhc_reinit,
Yangbo Lu982f4252019-06-21 11:42:27 +08001649};
Yangbo Lu982f4252019-06-21 11:42:27 +08001650
1651static struct esdhc_soc_data usdhc_imx7d_data = {
1652 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1653 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1654 | ESDHC_FLAG_HS400,
Yangbo Lu982f4252019-06-21 11:42:27 +08001655};
1656
Jorge Ramirez-Ortiz8239e822021-09-08 21:56:42 +03001657static struct esdhc_soc_data usdhc_imx7ulp_data = {
1658 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
Oleksandr Suvorovd4245c22021-09-08 21:56:43 +03001659 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1660 | ESDHC_FLAG_HS400,
Jorge Ramirez-Ortiz8239e822021-09-08 21:56:42 +03001661};
1662
Peng Fan457fe962019-07-10 09:35:28 +00001663static struct esdhc_soc_data usdhc_imx8qm_data = {
1664 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1665 ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1666 ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1667};
1668
Yangbo Lu982f4252019-06-21 11:42:27 +08001669static const struct udevice_id fsl_esdhc_ids[] = {
Fabio Estevameaf8ccc2021-02-15 08:58:15 -03001670 { .compatible = "fsl,imx51-esdhc", },
Yangbo Lu982f4252019-06-21 11:42:27 +08001671 { .compatible = "fsl,imx53-esdhc", },
1672 { .compatible = "fsl,imx6ul-usdhc", },
1673 { .compatible = "fsl,imx6sx-usdhc", },
1674 { .compatible = "fsl,imx6sl-usdhc", },
1675 { .compatible = "fsl,imx6q-usdhc", },
1676 { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
Jorge Ramirez-Ortiz8239e822021-09-08 21:56:42 +03001677 { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,},
Peng Fan457fe962019-07-10 09:35:28 +00001678 { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Peng Fand7689fa2019-11-04 17:31:17 +08001679 { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1680 { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Marek Vasut104704b2022-03-10 21:27:04 +01001681 { .compatible = "fsl,imx8mp-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Peng Fand7689fa2019-11-04 17:31:17 +08001682 { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
Giulio Benetti65b5ec12020-01-10 15:51:46 +01001683 { .compatible = "fsl,imxrt-usdhc", },
Yangbo Lu982f4252019-06-21 11:42:27 +08001684 { .compatible = "fsl,esdhc", },
1685 { /* sentinel */ }
1686};
1687
Yangbo Lu982f4252019-06-21 11:42:27 +08001688static int fsl_esdhc_bind(struct udevice *dev)
1689{
Simon Glassfa20e932020-12-03 16:55:20 -07001690 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu982f4252019-06-21 11:42:27 +08001691
1692 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1693}
Yangbo Lu982f4252019-06-21 11:42:27 +08001694
1695U_BOOT_DRIVER(fsl_esdhc) = {
Walter Lozano904b0be2020-07-29 12:31:16 -03001696 .name = "fsl_esdhc",
Yangbo Lu982f4252019-06-21 11:42:27 +08001697 .id = UCLASS_MMC,
1698 .of_match = fsl_esdhc_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -07001699 .of_to_plat = fsl_esdhc_of_to_plat,
Yangbo Lu982f4252019-06-21 11:42:27 +08001700 .ops = &fsl_esdhc_ops,
Yangbo Lu982f4252019-06-21 11:42:27 +08001701 .bind = fsl_esdhc_bind,
Yangbo Lu982f4252019-06-21 11:42:27 +08001702 .probe = fsl_esdhc_probe,
Simon Glass71fa5b42020-12-03 16:55:18 -07001703 .plat_auto = sizeof(struct fsl_esdhc_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -07001704 .priv_auto = sizeof(struct fsl_esdhc_priv),
Yangbo Lu982f4252019-06-21 11:42:27 +08001705};
Walter Lozano8aff6732020-07-29 12:31:17 -03001706
Simon Glassdf65db82020-12-28 20:34:57 -07001707DM_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
Yangbo Lu982f4252019-06-21 11:42:27 +08001708#endif