Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2008 |
| 4 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. |
| 5 | * |
| 6 | * Copyright 2008 Freescale Semiconductor, Inc. |
| 7 | * |
| 8 | * (C) Copyright 2000 |
| 9 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 10 | */ |
| 11 | |
Tom Rini | dec7ea0 | 2024-05-20 13:35:03 -0600 | [diff] [blame] | 12 | #include <config.h> |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 13 | #include <asm/fsl_law.h> |
| 14 | #include <asm/mmu.h> |
| 15 | |
| 16 | /* |
| 17 | * LAW(Local Access Window) configuration: |
| 18 | * |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 19 | * 0x0000_0000 0x2fff_ffff DDR 512M |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 20 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 21 | * 0xc000_0000 0xc00f_ffff FPGA 1M |
Anatolij Gustschin | e6f5c91 | 2008-08-15 15:42:13 +0200 | [diff] [blame] | 22 | * 0xc800_0000 0xcbff_ffff LIME 64M |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 23 | * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 24 | * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 25 | * 0xfc00_0000 0xffff_ffff FLASH 64M |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 26 | * |
| 27 | * Notes: |
| 28 | * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
| 29 | * If flash is 8M at default position (last 8M), no LAW needed. |
| 30 | */ |
| 31 | |
| 32 | struct law_entry law_table[] = { |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 33 | SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), |
| 34 | SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), |
| 35 | #if defined(CFG_SYS_FPGA_BASE) |
| 36 | SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), |
Sergei Poselenov | 96dd16b | 2008-06-06 15:42:41 +0200 | [diff] [blame] | 37 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 38 | SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), |
Sergei Poselenov | f2bf96c | 2008-04-30 11:42:50 +0200 | [diff] [blame] | 39 | }; |
| 40 | |
| 41 | int num_law_entries = ARRAY_SIZE(law_table); |