blob: f759ee364666ebaf9eeda7d4ea108eae555b5d16 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Hao Zhangc13cbcf2014-10-22 16:32:33 +03002/*
3 * K2L EVM : Board initialization
4 *
5 * (C) Copyright 2014
6 * Texas Instruments Incorporated, <www.ti.com>
Hao Zhangc13cbcf2014-10-22 16:32:33 +03007 */
8
9#include <common.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Hao Zhangc13cbcf2014-10-22 16:32:33 +030012#include <asm/arch/ddr3.h>
13#include <asm/arch/hardware.h>
Hao Zhang7874b8a2014-10-29 13:09:34 +020014#include <asm/ti-common/keystone_net.h>
Hao Zhangc13cbcf2014-10-22 16:32:33 +030015
Lokesh Vutlaa9a0e122017-05-03 16:58:26 +053016unsigned int get_external_clk(u32 clk)
17{
18 unsigned int clk_freq;
19
20 switch (clk) {
21 case sys_clk:
22 clk_freq = 122880000;
23 break;
24 case alt_core_clk:
25 clk_freq = 100000000;
26 break;
27 case pa_clk:
28 clk_freq = 122880000;
29 break;
30 case tetris_clk:
31 clk_freq = 122880000;
32 break;
33 case ddr3a_clk:
34 clk_freq = 100000000;
35 break;
36 default:
37 clk_freq = 0;
38 break;
39 }
40
41 return clk_freq;
42}
Hao Zhangc13cbcf2014-10-22 16:32:33 +030043
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053044static struct pll_init_data core_pll_config[NUM_SPDS] = {
45 [SPD800] = CORE_PLL_799,
46 [SPD1000] = CORE_PLL_1000,
Lokesh Vutlab4a96bd2015-08-17 19:58:34 +053047 [SPD1200] = CORE_PLL_1198,
Hao Zhangc13cbcf2014-10-22 16:32:33 +030048};
49
Lokesh Vutla70438fc2015-07-28 14:16:43 +053050s16 divn_val[16] = {
51 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
52};
53
Hao Zhangc13cbcf2014-10-22 16:32:33 +030054static struct pll_init_data tetris_pll_config[] = {
Lokesh Vutla9da9afa2015-07-28 14:16:44 +053055 [SPD800] = TETRIS_PLL_799,
56 [SPD1000] = TETRIS_PLL_1000,
57 [SPD1200] = TETRIS_PLL_1198,
58 [SPD1350] = TETRIS_PLL_1352,
59 [SPD1400] = TETRIS_PLL_1401,
Hao Zhangc13cbcf2014-10-22 16:32:33 +030060};
61
62static struct pll_init_data pa_pll_config =
63 PASS_PLL_983;
64
Lokesh Vutla79a94a22015-07-28 14:16:46 +053065struct pll_init_data *get_pll_init_data(int pll)
66{
67 int speed;
68 struct pll_init_data *data;
69
70 switch (pll) {
71 case MAIN_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060072 speed = get_max_dev_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053073 data = &core_pll_config[speed];
74 break;
75 case TETRIS_PLL:
Lokesh Vutlab35410e2016-03-04 10:36:40 -060076 speed = get_max_arm_speed(speeds);
Lokesh Vutla79a94a22015-07-28 14:16:46 +053077 data = &tetris_pll_config[speed];
78 break;
79 case PASS_PLL:
80 data = &pa_pll_config;
81 break;
82 default:
83 data = NULL;
84 }
85
86 return data;
87}
88
Hao Zhangc13cbcf2014-10-22 16:32:33 +030089#ifdef CONFIG_BOARD_EARLY_INIT_F
90int board_early_init_f(void)
91{
Lokesh Vutla79a94a22015-07-28 14:16:46 +053092 init_plls();
Hao Zhangc13cbcf2014-10-22 16:32:33 +030093
94 return 0;
95}
96#endif
97
Jean-Jacques Hiblot2037fa42017-09-15 12:57:24 +020098#if defined(CONFIG_MULTI_DTB_FIT)
Cooper Jr., Franklin43ff2242017-06-16 17:25:16 -050099int board_fit_config_name_match(const char *name)
100{
101 if (!strcmp(name, "keystone-k2l-evm"))
102 return 0;
103
104 return -1;
105}
106#endif
107
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300108#ifdef CONFIG_SPL_BUILD
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300109void spl_init_keystone_plls(void)
110{
Lokesh Vutla79a94a22015-07-28 14:16:46 +0530111 init_plls();
Hao Zhangc13cbcf2014-10-22 16:32:33 +0300112}
113#endif