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git01.mediatek.com / filogic / uboot / f3c633813c2c9620553a454df65f3587981c7f75 / . / arch / riscv / cpu / fu540 / Kconfig
blob: 05463b26258624d138595d1b2b84e6c54c92d65b [file] [log] [blame]
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]1# SPDX-License-Identifier: GPL-2.0+
2#
3# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
4
5config SIFIVE_FU540
6 bool
7 select ARCH_EARLY_INIT_R
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]8 select SUPPORT_SPL
9 select RAM
10 select SPL_RAM if SPL
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]11 imply CPU
12 imply CPU_RISCV
Sean Anderson9baaaef2020-09-28 10:52:21 -0400[diff] [blame]13 imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
Bin Meng614b1d82021-05-11 20:04:12 +0800[diff] [blame]14 imply SPL_SIFIVE_CLINT
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]15 imply CMD_CPU
Simon Glass2f002162021-03-15 18:11:18 +1300[diff] [blame]16 imply SPL_CPU
Pragnesh Patel25269c02020-05-29 11:33:34 +0530[diff] [blame]17 imply SPL_OPENSBI
18 imply SPL_LOAD_FIT
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]19 imply SMP
20 imply CLK_SIFIVE
Green Wanecefa5f2021-05-27 06:52:08 -0700[diff] [blame]21 imply CLK_SIFIVE_PRCI
Bin Meng6b155512020-08-02 23:09:04 -0700[diff] [blame]22 imply SIFIVE_SERIAL
23 imply MACB
24 imply MII
25 imply SPI
26 imply SPI_SIFIVE
27 imply MMC
28 imply MMC_SPI
29 imply MMC_BROKEN_CD
30 imply CMD_MMC
31 imply DM_GPIO
32 imply SIFIVE_GPIO
33 imply CMD_GPIO
34 imply MISC
35 imply SIFIVE_OTP
36 imply DM_PWM
37 imply PWM_SIFIVE
Pragnesh Patel4f1b4442020-11-14 14:42:35 +0530[diff] [blame]38 imply DM_I2C
39 imply SYS_I2C_OCORES
Jagan Tekie70ef902020-07-15 15:39:00 +0530[diff] [blame]40
41if ENV_IS_IN_SPI_FLASH
42
43config ENV_OFFSET
44 default 0x505000
45
46config ENV_SIZE
47 default 0x20000
48
49config ENV_SECT_SIZE
50 default 0x10000
51
52endif # ENV_IS_IN_SPI_FLASH