Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 2 | /* |
| 3 | * bur_am335x_common.h |
| 4 | * |
| 5 | * common parts used by B&R AM335x based boards |
| 6 | * |
Hannes Schmelzer | 27bf441 | 2016-02-19 12:09:45 +0100 | [diff] [blame] | 7 | * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> - |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 8 | * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __BUR_AM335X_COMMON_H__ |
| 12 | #define __BUR_AM335X_COMMON_H__ |
| 13 | /* ------------------------------------------------------------------------- */ |
Hannes Schmelzer | 5639eeb | 2018-07-06 15:41:28 +0200 | [diff] [blame] | 14 | |
| 15 | /* legacy #defines for non DM bur-board */ |
| 16 | #ifndef CONFIG_DM |
| 17 | #define CONFIG_SYS_NS16550_SERIAL |
| 18 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 19 | #define CONFIG_SYS_NS16550_CLK (48000000) |
| 20 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 |
| 21 | |
Hannes Schmelzer | 5639eeb | 2018-07-06 15:41:28 +0200 | [diff] [blame] | 22 | #endif /* CONFIG_DM */ |
| 23 | |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 24 | #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ |
| 25 | |
| 26 | /* Timer information */ |
| 27 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ |
| 28 | #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 29 | #define CONFIG_POWER_TPS65217 |
| 30 | |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 31 | #include <asm/arch/omap.h> |
| 32 | |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 33 | /* |
| 34 | * SPL related defines. The Public RAM memory map the ROM defines the |
| 35 | * area between 0x402F0400 and 0x4030B800 as a download area and |
| 36 | * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also |
| 37 | * supports X-MODEM loading via UART, and we leverage this and then use |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 38 | * Y-MODEM to load u-boot.img, when booted over UART. We must also include |
| 39 | * the scratch space that U-Boot uses in SRAM. |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 40 | */ |
Tom Rini | cfff4aa | 2016-08-26 13:30:43 -0400 | [diff] [blame] | 41 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
| 42 | CONFIG_SPL_TEXT_BASE) |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * Since SPL did pll and ddr initialization for us, |
| 46 | * we don't need to do it twice. |
| 47 | */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 48 | /* |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 49 | * ---------------------------------------------------------------------------- |
| 50 | * DDR information. We say (for simplicity) that we have 1 bank, |
| 51 | * always, even when we have more. We always start at 0x80000000, |
| 52 | * and we place the initial stack pointer in our SRAM. |
| 53 | */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 54 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| 55 | #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ |
| 56 | GENERATED_GBL_DATA_SIZE) |
| 57 | |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 58 | /* |
| 59 | * Our platforms make use of SPL to initalize the hardware (primarily |
| 60 | * memory) enough for full U-Boot to be loaded. We also support Falcon |
| 61 | * Mode so that the Linux kernel can be booted directly from SPL |
| 62 | * instead, if desired. We make use of the general SPL framework found |
| 63 | * under common/spl/. Given our generally common memory map, we set a |
| 64 | * number of related defaults and sizes here. |
| 65 | */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 66 | /* |
| 67 | * Place the image at the start of the ROM defined image space. |
| 68 | * We limit our size to the ROM-defined downloaded image area, and use the |
| 69 | * rest of the space for stack. We load U-Boot itself into memory at |
| 70 | * 0x80800000 for legacy reasons (to not conflict with older SPLs). We |
| 71 | * have our BSS be placed 1MiB after this, to allow for the default |
| 72 | * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. |
| 73 | * We have the SPL malloc pool at the end of the BSS area. |
| 74 | * |
| 75 | * ---------------------------------------------------------------------------- |
| 76 | */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 77 | #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 |
| 78 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ |
| 79 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| 80 | CONFIG_SPL_BSS_MAX_SIZE) |
| 81 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN |
| 82 | |
| 83 | /* General parts of the framework, required. */ |
Hannes Petermaier | fb00366 | 2014-02-07 08:07:36 +0100 | [diff] [blame] | 84 | |
| 85 | #endif /* ! __BUR_AM335X_COMMON_H__ */ |