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rev13@wp.pl6b5e5a92015-03-01 12:44:42 +01001/*
2 * (C) Copyright 2011, 2012, 2013
3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4 * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
5 * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
6 * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
7 *
8 * (C) Copyright 2015
Kamil Lulko75d48a62015-12-01 09:08:19 +01009 * Kamil Lulko, <kamil.lulko@gmail.com>
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010010 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -060015#include <dm.h>
Patrice Chotardf3a701a2017-12-12 09:49:39 +010016
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010017#include <asm/io.h>
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010018#include <asm/arch/stm32.h>
19#include <asm/arch/gpio.h>
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010020
21DECLARE_GLOBAL_DATA_PTR;
22
23const struct stm32_gpio_ctl gpio_ctl_gpout = {
24 .mode = STM32_GPIO_MODE_OUT,
25 .otype = STM32_GPIO_OTYPE_PP,
26 .speed = STM32_GPIO_SPEED_50M,
27 .pupd = STM32_GPIO_PUPD_NO,
28 .af = STM32_GPIO_AF0
29};
30
31const struct stm32_gpio_ctl gpio_ctl_usart = {
32 .mode = STM32_GPIO_MODE_AF,
33 .otype = STM32_GPIO_OTYPE_PP,
34 .speed = STM32_GPIO_SPEED_50M,
35 .pupd = STM32_GPIO_PUPD_UP,
kunhuahuang48482ce2015-04-28 03:01:19 +080036 .af = STM32_GPIO_USART
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010037};
38
kunhuahuang48482ce2015-04-28 03:01:19 +080039static const struct stm32_gpio_dsc usart_gpio[] = {
40 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_TX}, /* TX */
41 {STM32_GPIO_PORT_X, STM32_GPIO_PIN_RX}, /* RX */
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010042};
43
kunhuahuang48482ce2015-04-28 03:01:19 +080044int uart_setup_gpio(void)
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010045{
46 int i;
47 int rv = 0;
48
kunhuahuang48482ce2015-04-28 03:01:19 +080049 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) {
50 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart);
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +010051 if (rv)
52 goto out;
53 }
54
55out:
56 return rv;
57}
58
59const struct stm32_gpio_ctl gpio_ctl_fmc = {
60 .mode = STM32_GPIO_MODE_AF,
61 .otype = STM32_GPIO_OTYPE_PP,
62 .speed = STM32_GPIO_SPEED_100M,
63 .pupd = STM32_GPIO_PUPD_NO,
64 .af = STM32_GPIO_AF12
65};
66
67static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = {
68 /* Chip is LQFP144, see DM00077036.pdf for details */
69 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */
70 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */
71 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */
72 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */
73 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */
74 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */
75 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */
76 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */
77 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */
78 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */
79 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */
80 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */
81 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */
82 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */
83 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */
84 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */
85 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */
86 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */
87 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */
88 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */
89 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */
90 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */
91 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */
92 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */
93 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */
94 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */
95 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */
96 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */
97 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */
98 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */
99 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */
100 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */
101 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_6}, /* 136, SDRAM_NE */
102 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */
103 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */
104 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_0}, /* 26, SDRAM_NWE */
105 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_5}, /* 135, SDRAM_CKE */
106 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */
107};
108
109static int fmc_setup_gpio(void)
110{
111 int rv = 0;
112 int i;
113
114 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) {
115 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i],
116 &gpio_ctl_fmc);
117 if (rv)
118 goto out;
119 }
120
121out:
122 return rv;
123}
124
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100125int dram_init(void)
126{
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100127 int rv;
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100128 struct udevice *dev;
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100129
130 rv = fmc_setup_gpio();
131 if (rv)
132 return rv;
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100133 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
134 if (rv) {
135 debug("DRAM init failed: %d\n", rv);
136 return rv;
137 }
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100138
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100139 if (fdtdec_setup_memory_size() != 0)
140 rv = -EINVAL;
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100141
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100142 return rv;
143}
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100144
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100145int dram_init_banksize(void)
146{
147 fdtdec_setup_memory_banksize();
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100148
Patrice Chotardb59d10f2017-12-12 09:49:34 +0100149 return 0;
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100150}
151
152u32 get_board_rev(void)
153{
154 return 0;
155}
156
157int board_early_init_f(void)
158{
159 int res;
160
kunhuahuang48482ce2015-04-28 03:01:19 +0800161 res = uart_setup_gpio();
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100162 if (res)
163 return res;
rev13@wp.pl6b5e5a92015-03-01 12:44:42 +0100164 return 0;
165}
166
167int board_init(void)
168{
169 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
170
171 return 0;
172}
Antonio Borneo989e8b22015-07-19 22:19:46 +0800173
174#ifdef CONFIG_MISC_INIT_R
175int misc_init_r(void)
176{
177 char serialno[25];
178 uint32_t u_id_low, u_id_mid, u_id_high;
179
Simon Glass64b723f2017-08-03 12:22:12 -0600180 if (!env_get("serial#")) {
Antonio Borneo989e8b22015-07-19 22:19:46 +0800181 u_id_low = readl(&STM32_U_ID->u_id_low);
182 u_id_mid = readl(&STM32_U_ID->u_id_mid);
183 u_id_high = readl(&STM32_U_ID->u_id_high);
184 sprintf(serialno, "%08x%08x%08x",
185 u_id_high, u_id_mid, u_id_low);
Simon Glass6a38e412017-08-03 12:22:09 -0600186 env_set("serial#", serialno);
Antonio Borneo989e8b22015-07-19 22:19:46 +0800187 }
188
189 return 0;
190}
191#endif