blob: 431e87bac47ffa8b51bd37cc6d2e6393352ba613 [file] [log] [blame]
Sergey Kubushyne8f39122007-08-10 20:26:18 +02001/*
2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
3 *
4 * Based on:
5 *
6 * -------------------------------------------------------------------------
7 *
8 * linux/include/asm-arm/arch-davinci/hardware.h
9 *
10 * Copyright (C) 2006 Texas Instruments.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *
32 */
33#ifndef __ASM_ARCH_HARDWARE_H
34#define __ASM_ARCH_HARDWARE_H
35
36#include <config.h>
37#include <asm/sizes.h>
38
39#define REG(addr) (*(volatile unsigned int *)(addr))
40#define REG_P(addr) ((volatile unsigned int *)(addr))
41
42typedef volatile unsigned int dv_reg;
43typedef volatile unsigned int * dv_reg_p;
44
45/*
46 * Base register addresses
David Brownell6f7e6392009-05-15 23:44:09 +020047 *
48 * NOTE: some of these DM6446-specific addresses DO NOT WORK
49 * on other DaVinci chips. Double check them before you try
50 * using the addresses ... or PSC module identifiers, etc.
Sergey Kubushyne8f39122007-08-10 20:26:18 +020051 */
Nick Thompson4c1e5092009-11-12 11:06:08 -050052#ifndef CONFIG_SOC_DA8XX
53
Sergey Kubushyne8f39122007-08-10 20:26:18 +020054#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
55#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
56#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
57#define DAVINCI_UART0_BASE (0x01c20000)
58#define DAVINCI_UART1_BASE (0x01c20400)
Sergey Kubushyne8f39122007-08-10 20:26:18 +020059#define DAVINCI_I2C_BASE (0x01c21000)
60#define DAVINCI_TIMER0_BASE (0x01c21400)
61#define DAVINCI_TIMER1_BASE (0x01c21800)
62#define DAVINCI_WDOG_BASE (0x01c21c00)
63#define DAVINCI_PWM0_BASE (0x01c22000)
64#define DAVINCI_PWM1_BASE (0x01c22400)
65#define DAVINCI_PWM2_BASE (0x01c22800)
66#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
67#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
68#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
69#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
Sergey Kubushyne8f39122007-08-10 20:26:18 +020070#define DAVINCI_ARM_INTC_BASE (0x01c48000)
Sergey Kubushyne8f39122007-08-10 20:26:18 +020071#define DAVINCI_USB_OTG_BASE (0x01c64000)
72#define DAVINCI_CFC_ATA_BASE (0x01c66000)
73#define DAVINCI_SPI_BASE (0x01c66800)
74#define DAVINCI_GPIO_BASE (0x01c67000)
Sergey Kubushyne8f39122007-08-10 20:26:18 +020075#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
Sandeep Paulraj766dd332009-10-13 12:32:32 -040076#if !defined(CONFIG_SOC_DM646X)
Sergey Kubushyne8f39122007-08-10 20:26:18 +020077#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
78#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
79#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
80#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
Sandeep Paulraj766dd332009-10-13 12:32:32 -040081#endif
s-paulraj@ti.com5bcea062009-05-15 23:48:36 +020082#define DAVINCI_DDR_BASE (0x80000000)
David Brownell6f7e6392009-05-15 23:44:09 +020083
84#ifdef CONFIG_SOC_DM644X
85#define DAVINCI_UART2_BASE 0x01c20800
86#define DAVINCI_UHPI_BASE 0x01c67800
87#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
88#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
89#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
90#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
91#define DAVINCI_IMCOP_BASE 0x01cc0000
92#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
93#define DAVINCI_VLYNQ_BASE 0x01e01000
94#define DAVINCI_ASP_BASE 0x01e02000
95#define DAVINCI_MMC_SD_BASE 0x01e10000
96#define DAVINCI_MS_BASE 0x01e20000
97#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
98
99#elif defined(CONFIG_SOC_DM355)
100#define DAVINCI_MMC_SD1_BASE 0x01e00000
101#define DAVINCI_ASP0_BASE 0x01e02000
102#define DAVINCI_ASP1_BASE 0x01e04000
103#define DAVINCI_UART2_BASE 0x01e06000
104#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
105#define DAVINCI_MMC_SD0_BASE 0x01e11000
106
s-paulraj@ti.com5bcea062009-05-15 23:48:36 +0200107#elif defined(CONFIG_SOC_DM365)
108#define DAVINCI_MMC_SD1_BASE 0x01d00000
109#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
110#define DAVINCI_MMC_SD0_BASE 0x01d11000
111
Sandeep Paulrajb7a6b432009-09-08 11:37:39 -0400112#elif defined(CONFIG_SOC_DM646X)
113#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
114#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
115#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
116#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
117#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
118
David Brownell6f7e6392009-05-15 23:44:09 +0200119#endif
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200120
Nick Thompson4c1e5092009-11-12 11:06:08 -0500121#else /* CONFIG_SOC_DA8XX */
122
123#define DAVINCI_UART0_BASE 0x01c42000
124#define DAVINCI_UART1_BASE 0x01d0c000
125#define DAVINCI_UART2_BASE 0x01d0d000
126#define DAVINCI_I2C0_BASE 0x01c22000
127#define DAVINCI_I2C1_BASE 0x01e28000
128#define DAVINCI_TIMER0_BASE 0x01c20000
129#define DAVINCI_TIMER1_BASE 0x01c21000
130#define DAVINCI_WDOG_BASE 0x01c21000
Heiko Schocher20409912011-09-14 19:48:22 +0000131#define DAVINCI_RTC_BASE 0x01c23000
Nick Thompson4c1e5092009-11-12 11:06:08 -0500132#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -0400133#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
Nick Thompson4c1e5092009-11-12 11:06:08 -0500134#define DAVINCI_PSC0_BASE 0x01c10000
135#define DAVINCI_PSC1_BASE 0x01e27000
136#define DAVINCI_SPI0_BASE 0x01c41000
137#define DAVINCI_USB_OTG_BASE 0x01e00000
Stefano Babicfc850ab2010-11-11 15:38:02 +0100138#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
139 0x01e12000 : 0x01f0e000)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500140#define DAVINCI_GPIO_BASE 0x01e26000
141#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
142#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
143#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
144#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
Heiko Schochera9c49092011-09-14 19:59:33 +0000145#define DAVINCI_SYSCFG1_BASE 0x01e2c000
Laurence Withers85173762011-07-18 09:53:17 -0400146#define DAVINCI_MMC_SD0_BASE 0x01c40000
147#define DAVINCI_MMC_SD1_BASE 0x01e1b000
Heiko Schocher4b8ccec2011-09-14 19:44:01 +0000148#define DAVINCI_TIMER2_BASE 0x01f0c000
149#define DAVINCI_TIMER3_BASE 0x01f0d000
Nick Thompson4c1e5092009-11-12 11:06:08 -0500150#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
151#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
152#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
153#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
154#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
155#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
156#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
157#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
158#define DAVINCI_INTC_BASE 0xfffee000
159#define DAVINCI_BOOTCFG_BASE 0x01c14000
Nagabhushana Netagunte24d30962011-09-03 22:19:28 -0400160#define DAVINCI_L3CBARAM_BASE 0x80000000
Sudhakar Rajashekhara7bf91d72010-11-11 15:38:01 +0100161#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
Nagabhushana Netagunte24d30962011-09-03 22:19:28 -0400162#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
163#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
164#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500165
Nagabhushana Netagunte63e201f2011-09-03 22:21:04 -0400166#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
167#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
168#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
169#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
Sudhakar Rajashekhara5851e122010-11-18 09:59:37 -0500170#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
171#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
172#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
173#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500174#endif /* CONFIG_SOC_DA8XX */
175
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200176/* Power and Sleep Controller (PSC) Domains */
177#define DAVINCI_GPSC_ARMDOMAIN 0
178#define DAVINCI_GPSC_DSPDOMAIN 1
179
Nick Thompson4c1e5092009-11-12 11:06:08 -0500180#ifndef CONFIG_SOC_DA8XX
181
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200182#define DAVINCI_LPSC_VPSSMSTR 0
183#define DAVINCI_LPSC_VPSSSLV 1
184#define DAVINCI_LPSC_TPCC 2
185#define DAVINCI_LPSC_TPTC0 3
186#define DAVINCI_LPSC_TPTC1 4
187#define DAVINCI_LPSC_EMAC 5
188#define DAVINCI_LPSC_EMAC_WRAPPER 6
189#define DAVINCI_LPSC_MDIO 7
190#define DAVINCI_LPSC_IEEE1394 8
191#define DAVINCI_LPSC_USB 9
192#define DAVINCI_LPSC_ATA 10
193#define DAVINCI_LPSC_VLYNQ 11
194#define DAVINCI_LPSC_UHPI 12
195#define DAVINCI_LPSC_DDR_EMIF 13
196#define DAVINCI_LPSC_AEMIF 14
197#define DAVINCI_LPSC_MMC_SD 15
198#define DAVINCI_LPSC_MEMSTICK 16
199#define DAVINCI_LPSC_McBSP 17
200#define DAVINCI_LPSC_I2C 18
201#define DAVINCI_LPSC_UART0 19
202#define DAVINCI_LPSC_UART1 20
203#define DAVINCI_LPSC_UART2 21
204#define DAVINCI_LPSC_SPI 22
205#define DAVINCI_LPSC_PWM0 23
206#define DAVINCI_LPSC_PWM1 24
207#define DAVINCI_LPSC_PWM2 25
208#define DAVINCI_LPSC_GPIO 26
209#define DAVINCI_LPSC_TIMER0 27
210#define DAVINCI_LPSC_TIMER1 28
211#define DAVINCI_LPSC_TIMER2 29
212#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
213#define DAVINCI_LPSC_ARM 31
214#define DAVINCI_LPSC_SCR2 32
215#define DAVINCI_LPSC_SCR3 33
216#define DAVINCI_LPSC_SCR4 34
217#define DAVINCI_LPSC_CROSSBAR 35
218#define DAVINCI_LPSC_CFG27 36
219#define DAVINCI_LPSC_CFG3 37
220#define DAVINCI_LPSC_CFG5 38
221#define DAVINCI_LPSC_GEM 39
222#define DAVINCI_LPSC_IMCOP 40
223
Sandeep Paulrajb7a6b432009-09-08 11:37:39 -0400224#define DAVINCI_DM646X_LPSC_EMAC 14
225#define DAVINCI_DM646X_LPSC_UART0 26
226#define DAVINCI_DM646X_LPSC_I2C 31
Sandeep Paulraj0f450952010-12-28 17:38:22 -0500227#define DAVINCI_DM646X_LPSC_TIMER0 34
Sandeep Paulrajb7a6b432009-09-08 11:37:39 -0400228
Nick Thompson4c1e5092009-11-12 11:06:08 -0500229#else /* CONFIG_SOC_DA8XX */
230
Laurence Withersb7ad1252011-07-18 09:53:19 -0400231#define DAVINCI_LPSC_TPCC 0
232#define DAVINCI_LPSC_TPTC0 1
233#define DAVINCI_LPSC_TPTC1 2
234#define DAVINCI_LPSC_AEMIF 3
235#define DAVINCI_LPSC_SPI0 4
236#define DAVINCI_LPSC_MMC_SD 5
237#define DAVINCI_LPSC_AINTC 6
238#define DAVINCI_LPSC_ARM_RAM_ROM 7
239#define DAVINCI_LPSC_SECCTL_KEYMGR 8
240#define DAVINCI_LPSC_UART0 9
241#define DAVINCI_LPSC_SCR0 10
242#define DAVINCI_LPSC_SCR1 11
243#define DAVINCI_LPSC_SCR2 12
244#define DAVINCI_LPSC_DMAX 13
245#define DAVINCI_LPSC_ARM 14
246#define DAVINCI_LPSC_GEM 15
247
248/* for LPSCs in PSC1, offset from 32 for differentiation */
249#define DAVINCI_LPSC_PSC1_BASE 32
Laurence Withers5871d342011-07-18 09:53:23 -0400250#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
251#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
Laurence Withersb7ad1252011-07-18 09:53:19 -0400252#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
253#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
254#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
255#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
256#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
Laurence Withersb7ad1252011-07-18 09:53:19 -0400257#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
258#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
259#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
260#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
Laurence Withers5871d342011-07-18 09:53:23 -0400261#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
262#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
Heiko Schocher3fcb59e2011-09-27 19:40:41 +0000263#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
Laurence Withers5871d342011-07-18 09:53:23 -0400264#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
265#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
266
267/* DA830-specific peripherals */
268#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
269#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
270#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
271#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
272#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
273#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
274
275/* DA850-specific peripherals */
276#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
277#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
278#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
279#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
280#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
281#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
282#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
283#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
284#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
285#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
286#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
287#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
288#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
289#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
290#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500291
292#endif /* CONFIG_SOC_DA8XX */
293
David Brownell3e030292009-05-15 23:44:06 +0200294void lpsc_on(unsigned int id);
295void dsp_on(void);
296
297void davinci_enable_uart0(void);
298void davinci_enable_emac(void);
299void davinci_enable_i2c(void);
300void davinci_errata_workarounds(void);
301
Nick Thompson4c1e5092009-11-12 11:06:08 -0500302#ifndef CONFIG_SOC_DA8XX
303
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200304/* Some PSC defines */
305#define PSC_CHP_SHRTSW (0x01c40038)
306#define PSC_GBLCTL (0x01c41010)
307#define PSC_EPCPR (0x01c41070)
308#define PSC_EPCCR (0x01c41078)
309#define PSC_PTCMD (0x01c41120)
310#define PSC_PTSTAT (0x01c41128)
311#define PSC_PDSTAT (0x01c41200)
312#define PSC_PDSTAT1 (0x01c41204)
313#define PSC_PDCTL (0x01c41300)
314#define PSC_PDCTL1 (0x01c41304)
315
316#define PSC_MDCTL_BASE (0x01c41a00)
317#define PSC_MDSTAT_BASE (0x01c41800)
318
319#define VDD3P3V_PWDN (0x01c40048)
320#define UART0_PWREMU_MGMT (0x01c20030)
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200321
322#define PSC_SILVER_BULLET (0x01c41a20)
323
Nick Thompson4c1e5092009-11-12 11:06:08 -0500324#else /* CONFIG_SOC_DA8XX */
325
Heiko Schochereed7ac52011-09-14 19:59:34 +0000326#define PSC_ENABLE 0x3
327#define PSC_DISABLE 0x2
328#define PSC_SYNCRESET 0x1
329#define PSC_SWRSTDISABLE 0x0
330
Nick Thompson4c1e5092009-11-12 11:06:08 -0500331#define PSC_PSC0_MODULE_ID_CNT 16
332#define PSC_PSC1_MODULE_ID_CNT 32
333
334struct davinci_psc_regs {
335 dv_reg revid;
336 dv_reg rsvd0[71];
337 dv_reg ptcmd;
338 dv_reg rsvd1;
339 dv_reg ptstat;
340 dv_reg rsvd2[437];
341 union {
342 struct {
343 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
344 dv_reg rsvd3[112];
345 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
346 } psc0;
347 struct {
348 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
349 dv_reg rsvd3[96];
350 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
351 } psc1;
352 };
353};
354
355#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
356#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
357
358#endif /* CONFIG_SOC_DA8XX */
359
Sergei Shtylyov617ee0b2011-09-23 04:29:15 +0000360#define PSC_MDSTAT_STATE 0x3f
361
Nick Thompson4c1e5092009-11-12 11:06:08 -0500362#ifndef CONFIG_SOC_DA8XX
363
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200364/* Miscellania... */
365#define VBPR (0x20000020)
David Brownell6f7e6392009-05-15 23:44:09 +0200366
367/* NOTE: system control modules are *highly* chip-specific, both
368 * as to register content (e.g. for muxing) and which registers exist.
369 */
370#define PINMUX0 0x01c40000
371#define PINMUX1 0x01c40004
372#define PINMUX2 0x01c40008
373#define PINMUX3 0x01c4000c
374#define PINMUX4 0x01c40010
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200375
Nick Thompson4c1e5092009-11-12 11:06:08 -0500376#else /* CONFIG_SOC_DA8XX */
377
378struct davinci_pllc_regs {
379 dv_reg revid;
380 dv_reg rsvd1[56];
381 dv_reg rstype;
382 dv_reg rsvd2[6];
383 dv_reg pllctl;
384 dv_reg ocsel;
385 dv_reg rsvd3[2];
386 dv_reg pllm;
387 dv_reg prediv;
388 dv_reg plldiv1;
389 dv_reg plldiv2;
390 dv_reg plldiv3;
391 dv_reg oscdiv;
392 dv_reg postdiv;
393 dv_reg rsvd4[3];
394 dv_reg pllcmd;
395 dv_reg pllstat;
396 dv_reg alnctl;
397 dv_reg dchange;
398 dv_reg cken;
399 dv_reg ckstat;
400 dv_reg systat;
401 dv_reg rsvd5[3];
402 dv_reg plldiv4;
403 dv_reg plldiv5;
404 dv_reg plldiv6;
405 dv_reg plldiv7;
406 dv_reg rsvd6[32];
407 dv_reg emucnt0;
408 dv_reg emucnt1;
409};
410
Sudhakar Rajashekhara0a7fbec2011-09-03 22:18:04 -0400411#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
412#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500413#define DAVINCI_PLLC_DIV_MASK 0x1f
414
Stefano Babicfc850ab2010-11-11 15:38:02 +0100415#define ASYNC3 get_async3_src()
416#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
417#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500418/* Clock IDs */
419enum davinci_clk_ids {
420 DAVINCI_SPI0_CLKID = 2,
421 DAVINCI_UART2_CLKID = 2,
422 DAVINCI_MDIO_CLKID = 4,
423 DAVINCI_ARM_CLKID = 6,
424 DAVINCI_PLLM_CLKID = 0xff,
425 DAVINCI_PLLC_CLKID = 0x100,
426 DAVINCI_AUXCLK_CLKID = 0x101
427};
428
429int clk_get(enum davinci_clk_ids id);
430
431/* Boot config */
432struct davinci_syscfg_regs {
433 dv_reg revid;
Sughosh Ganu1b9c52b2010-11-30 11:25:01 -0500434 dv_reg rsvd[13];
435 dv_reg kick0;
436 dv_reg kick1;
437 dv_reg rsvd1[56];
Nick Thompson4c1e5092009-11-12 11:06:08 -0500438 dv_reg pinmux[20];
439 dv_reg suspsrc;
440 dv_reg chipsig;
441 dv_reg chipsig_clr;
442 dv_reg cfgchip0;
443 dv_reg cfgchip1;
444 dv_reg cfgchip2;
445 dv_reg cfgchip3;
446 dv_reg cfgchip4;
447};
448
449#define davinci_syscfg_regs \
450 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
451
452/* Emulation suspend bits */
453#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
454#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
455#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530456#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
Nick Thompson4c1e5092009-11-12 11:06:08 -0500457#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
458#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
459
Heiko Schochera9c49092011-09-14 19:59:33 +0000460struct davinci_syscfg1_regs {
461 dv_reg vtpio_ctl;
462 dv_reg ddr_slew;
463 dv_reg deepsleep;
464 dv_reg pupd_ena;
465 dv_reg pupd_sel;
466 dv_reg rxactive;
467 dv_reg pwrdwn;
468};
469
470#define davinci_syscfg1_regs \
471 ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
472
473#define DDR_SLEW_CMOSEN_BIT 4
474
Heiko Schochereed7ac52011-09-14 19:59:34 +0000475#define VTP_POWERDWN (1 << 6)
476#define VTP_LOCK (1 << 7)
477#define VTP_CLKRZ (1 << 13)
478#define VTP_READY (1 << 15)
479#define VTP_IOPWRDWN (1 << 14)
480
Nick Thompson4c1e5092009-11-12 11:06:08 -0500481/* Interrupt controller */
482struct davinci_aintc_regs {
483 dv_reg revid;
484 dv_reg cr;
485 dv_reg dummy0[2];
486 dv_reg ger;
487 dv_reg dummy1[219];
488 dv_reg ecr1;
489 dv_reg ecr2;
490 dv_reg ecr3;
491 dv_reg dummy2[1117];
492 dv_reg hier;
493};
494
495#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
496
497struct davinci_uart_ctrl_regs {
498 dv_reg revid1;
499 dv_reg revid2;
500 dv_reg pwremu_mgmt;
501 dv_reg mdr;
502};
503
504#define DAVINCI_UART_CTRL_BASE 0x28
505#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
506#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
507#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
508
509#define davinci_uart0_ctrl_regs \
510 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
511#define davinci_uart1_ctrl_regs \
512 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
513#define davinci_uart2_ctrl_regs \
514 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
515
516/* UART PWREMU_MGMT definitions */
517#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
518#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
519#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
520
Sudhakar Rajashekhara7bf91d72010-11-11 15:38:01 +0100521static inline int cpu_is_da830(void)
522{
523 unsigned int jtag_id = REG(JTAG_ID_REG);
524 unsigned short part_no = (jtag_id >> 12) & 0xffff;
525
526 return ((part_no == 0xb7df) ? 1 : 0);
527}
528static inline int cpu_is_da850(void)
529{
530 unsigned int jtag_id = REG(JTAG_ID_REG);
531 unsigned short part_no = (jtag_id >> 12) & 0xffff;
532
533 return ((part_no == 0xb7d1) ? 1 : 0);
534}
535
Stefano Babicfc850ab2010-11-11 15:38:02 +0100536static inline int get_async3_src(void)
537{
538 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
539 PLL1_SYSCLK2 : 2;
540}
541
Nick Thompson4c1e5092009-11-12 11:06:08 -0500542#endif /* CONFIG_SOC_DA8XX */
543
Sergey Kubushyne8f39122007-08-10 20:26:18 +0200544#endif /* __ASM_ARCH_HARDWARE_H */