| commit | 63e201f90364ea79eae7686022eac0e195a44704 | [log] [tgz] |
|---|---|---|
| author | Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> | Sat Sep 03 22:21:04 2011 -0400 |
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | Sun Sep 04 11:36:19 2011 +0200 |
| tree | 91a2566d7d9f01c2920e00042d77a7364e40fd28 | |
| parent | a33bc4b053305824a7eb8512ef38507c1d42b9c9 [diff] |
da850: modifications for Logic PD Rev.3 AM18xx EVM AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>