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git01.mediatek.com / filogic / uboot / f32a6f2eaf5bdd373c6847b38cc711836b4b1127 / . / configs / x530_defconfig
blob: 89612be631e3bacfecb89acd50775c5d7fac27ff [file] [log] [blame]
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]1CONFIG_ARM=y
Adam Fordd36b1022019-08-14 08:29:25 -0500[diff] [blame]2CONFIG_ARCH_CPU_INIT=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]3CONFIG_ARCH_MVEBU=y
Simon Glass72cc5382022-10-20 18:22:39 -0600[diff] [blame]4CONFIG_TEXT_BASE=0x00800000
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]5CONFIG_SPL_LIBCOMMON_SUPPORT=y
6CONFIG_SPL_LIBGENERIC_SUPPORT=y
Tom Rini2e262c42020-08-10 15:31:07 -0400[diff] [blame]7CONFIG_NR_DRAM_BANKS=2
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]8CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
9CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]10CONFIG_TARGET_X530=y
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]11CONFIG_SF_DEFAULT_SPEED=50000000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]12CONFIG_ENV_SIZE=0x10000
13CONFIG_ENV_OFFSET=0x100000
Tom Rini47dece32020-04-28 16:15:47 -0400[diff] [blame]14CONFIG_ENV_SECT_SIZE=0x40000
Tom Rinia20e51f2021-06-28 10:17:29 -0400[diff] [blame]15CONFIG_DEFAULT_DEVICE_TREE="armada-385-atl-x530"
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16CONFIG_SPL_SERIAL=y
Tom Rini9924ca12023-02-17 09:58:06 -0500[diff] [blame]17CONFIG_SPL_STACK=0x4002c000
Tom Rini27280b62024-11-12 13:45:12 -0600[diff] [blame]18CONFIG_SPL_TEXT_BASE=0x40000030
Tom Rinib9dc6842024-04-22 17:24:09 -0600[diff] [blame]19CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
20CONFIG_SPL_BSS_START_ADDR=0x40023000
21CONFIG_SPL_BSS_MAX_SIZE=0x4000
Tom Rinic427a582024-10-08 09:18:32 -0600[diff] [blame]22CONFIG_SYS_LOAD_ADDR=0x1000000
23CONFIG_SF_DEFAULT_BUS=1
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]24CONFIG_SPL=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]25CONFIG_DEBUG_UART_BASE=0xf1012000
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]26CONFIG_DEBUG_UART_CLOCK=250000000
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]27CONFIG_ENV_ADDR=0x100000
Tom Rinia77d6f82023-05-01 11:50:26 -0400[diff] [blame]28CONFIG_PCI=y
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]29CONFIG_DEBUG_UART=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]30CONFIG_FIT=y
31CONFIG_FIT_VERBOSE=y
Tom Rini914a8c02024-01-03 09:26:16 -0500[diff] [blame]32CONFIG_SYS_CBSIZE=256
33CONFIG_SYS_PBSIZE=276
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]34CONFIG_SILENT_CONSOLE=y
35CONFIG_SILENT_U_BOOT_ONLY=y
36CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC=y
Tom Rini36f48792021-10-30 23:03:57 -0400[diff] [blame]37CONFIG_DISPLAY_BOARDINFO_LATE=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]38CONFIG_MISC_INIT_R=y
Tom Riniabb0f522022-05-16 17:20:26 -0400[diff] [blame]39CONFIG_SPL_MAX_SIZE=0x22fd0
Chris Packham17ca1432019-02-18 10:30:54 +1300[diff] [blame]40CONFIG_SPL_BOARD_INIT=y
Tom Rinie7d67a42022-05-20 12:36:05 -0400[diff] [blame]41CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Tom Rini8a14ac42022-05-26 13:13:21 -0400[diff] [blame]42# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
Simon Glass1ba1d4e2021-07-10 21:14:28 -0600[diff] [blame]43CONFIG_SPL_WATCHDOG=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]44CONFIG_CMD_MEMINFO=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]45CONFIG_CMD_GPIO=y
46CONFIG_CMD_I2C=y
Tom Rini32c75d62020-05-26 15:06:18 -0400[diff] [blame]47CONFIG_CMD_PCI=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]48CONFIG_CMD_SPI=y
49CONFIG_CMD_USB=y
50# CONFIG_CMD_SETEXPR is not set
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]51CONFIG_CMD_TFTPPUT=y
Tom Rini27280b62024-11-12 13:45:12 -0600[diff] [blame]52CONFIG_CMD_DHCP=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]53CONFIG_CMD_MII=y
54CONFIG_CMD_PING=y
55CONFIG_CMD_CACHE=y
56CONFIG_CMD_TIME=y
57CONFIG_CMD_EXT2=y
58CONFIG_CMD_EXT4=y
59CONFIG_CMD_FAT=y
60CONFIG_CMD_FS_GENERIC=y
Tom Rini32c75d62020-05-26 15:06:18 -0400[diff] [blame]61CONFIG_CMD_MTDPARTS=y
Patrick Delaunaya6a44392022-12-07 09:26:41 +0100[diff] [blame]62CONFIG_MTDIDS_DEFAULT="nand0=nand"
63CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)"
Tom Rini32c75d62020-05-26 15:06:18 -0400[diff] [blame]64CONFIG_CMD_UBI=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]65CONFIG_ENV_OVERWRITE=y
Tom Rinia8a77502022-03-11 09:12:01 -0500[diff] [blame]66CONFIG_ARP_TIMEOUT=200
Tom Rini26011a32022-03-11 09:12:02 -0500[diff] [blame]67CONFIG_NET_RETRY_COUNT=50
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]68CONFIG_SPL_OF_TRANSLATE=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]69CONFIG_DM_I2C=y
70CONFIG_SYS_I2C_MVTWSI=y
71CONFIG_I2C_MUX=y
72CONFIG_I2C_MUX_PCA954x=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]73# CONFIG_MMC is not set
Miquel Raynald0935362019-10-03 19:50:03 +0200[diff] [blame]74CONFIG_MTD_RAW_NAND=y
Stefan Roese23b37f92019-08-22 12:28:04 +0200[diff] [blame]75CONFIG_SYS_NAND_USE_FLASH_BBT=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]76CONFIG_NAND_PXA3XX=y
Tom Rinifdae0072021-09-22 14:50:34 -0400[diff] [blame]77CONFIG_SYS_NAND_ONFI_DETECTION=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]78CONFIG_SPI_FLASH_MACRONIX=y
79CONFIG_SPI_FLASH_STMICRO=y
80CONFIG_SPI_FLASH_SST=y
Stefan Roese3179ec62019-01-25 11:52:43 +0100[diff] [blame]81CONFIG_PCI_MVEBU=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]82CONFIG_DM_RTC=y
83CONFIG_RTC_DS1307=y
Tom Rini37576b62020-06-16 19:06:21 -0400[diff] [blame]84CONFIG_SPECIFY_CONSOLE_INDEX=y
Pali Rohár40954732022-05-09 20:17:07 +0200[diff] [blame]85CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]86CONFIG_DEBUG_UART_SHIFT=2
87CONFIG_SYS_NS16550=y
88CONFIG_KIRKWOOD_SPI=y
89CONFIG_USB=y
Chris Packhamb55b2c92019-01-10 21:01:00 +1300[diff] [blame]90CONFIG_USB_EHCI_HCD=y
91CONFIG_USB_STORAGE=y
92CONFIG_USB_HOST_ETHER=y
93CONFIG_USB_ETHER_ASIX=y
94CONFIG_USB_ETHER_ASIX88179=y
Chris Packham17ca1432019-02-18 10:30:54 +1300[diff] [blame]95CONFIG_WDT=y
96CONFIG_WDT_ORION=y
Stefan Roese691aa9c2021-05-12 09:18:37 +0200[diff] [blame]97CONFIG_SPL_TINY_MEMSET=y