| Simon Glass | dcfac35 | 2014-11-12 22:42:15 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Google, Inc |
| 3 | * |
| 4 | * From Coreboot src/southbridge/intel/bd82x6x/pch.h |
| 5 | * |
| 6 | * Copyright (C) 2008-2009 coresystems GmbH |
| 7 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0 |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ASM_ARCH_PCH_H |
| 13 | #define _ASM_ARCH_PCH_H |
| 14 | |
| 15 | #include <pci.h> |
| 16 | |
| 17 | /* PCI Configuration Space (D31:F0): LPC */ |
| 18 | #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) |
| 19 | |
| 20 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 21 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 22 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 23 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 24 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 25 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 26 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 27 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 28 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 29 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 30 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 31 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
| 32 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 33 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 34 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 35 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
| 36 | #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) |
| 37 | |
| Simon Glass | f226c41 | 2014-11-12 22:42:19 -0700 | [diff] [blame^] | 38 | #define DEFAULT_RCBA 0xfed1c000 |
| 39 | |
| 40 | /* Root Complex Register Block */ |
| 41 | #define RCB_REG(reg) (DEFAULT_RCBA + (reg)) |
| 42 | |
| 43 | #define PCH_RCBA_BASE 0xf0 |
| 44 | |
| 45 | #define VCH 0x0000 /* 32bit */ |
| 46 | #define VCAP1 0x0004 /* 32bit */ |
| 47 | #define VCAP2 0x0008 /* 32bit */ |
| 48 | #define PVC 0x000c /* 16bit */ |
| 49 | #define PVS 0x000e /* 16bit */ |
| 50 | |
| 51 | #define V0CAP 0x0010 /* 32bit */ |
| 52 | #define V0CTL 0x0014 /* 32bit */ |
| 53 | #define V0STS 0x001a /* 16bit */ |
| 54 | |
| 55 | #define V1CAP 0x001c /* 32bit */ |
| 56 | #define V1CTL 0x0020 /* 32bit */ |
| 57 | #define V1STS 0x0026 /* 16bit */ |
| 58 | |
| 59 | #define RCTCL 0x0100 /* 32bit */ |
| 60 | #define ESD 0x0104 /* 32bit */ |
| 61 | #define ULD 0x0110 /* 32bit */ |
| 62 | #define ULBA 0x0118 /* 64bit */ |
| 63 | |
| 64 | #define RP1D 0x0120 /* 32bit */ |
| 65 | #define RP1BA 0x0128 /* 64bit */ |
| 66 | #define RP2D 0x0130 /* 32bit */ |
| 67 | #define RP2BA 0x0138 /* 64bit */ |
| 68 | #define RP3D 0x0140 /* 32bit */ |
| 69 | #define RP3BA 0x0148 /* 64bit */ |
| 70 | #define RP4D 0x0150 /* 32bit */ |
| 71 | #define RP4BA 0x0158 /* 64bit */ |
| 72 | #define HDD 0x0160 /* 32bit */ |
| 73 | #define HDBA 0x0168 /* 64bit */ |
| 74 | #define RP5D 0x0170 /* 32bit */ |
| 75 | #define RP5BA 0x0178 /* 64bit */ |
| 76 | #define RP6D 0x0180 /* 32bit */ |
| 77 | #define RP6BA 0x0188 /* 64bit */ |
| 78 | |
| 79 | #define RPC 0x0400 /* 32bit */ |
| 80 | #define RPFN 0x0404 /* 32bit */ |
| 81 | |
| 82 | #define SPI_FREQ_SWSEQ 0x3893 |
| 83 | #define SPI_DESC_COMP0 0x38b0 |
| 84 | #define SPI_FREQ_WR_ERA 0x38b4 |
| 85 | #define SOFT_RESET_CTRL 0x38f4 |
| 86 | #define SOFT_RESET_DATA 0x38f8 |
| 87 | |
| 88 | #define RC 0x3400 /* 32bit */ |
| 89 | #define HPTC 0x3404 /* 32bit */ |
| 90 | #define GCS 0x3410 /* 32bit */ |
| 91 | #define BUC 0x3414 /* 32bit */ |
| 92 | #define PCH_DISABLE_GBE (1 << 5) |
| 93 | #define FD 0x3418 /* 32bit */ |
| 94 | #define DISPBDF 0x3424 /* 16bit */ |
| 95 | #define FD2 0x3428 /* 32bit */ |
| 96 | #define CG 0x341c /* 32bit */ |
| 97 | |
| Simon Glass | dcfac35 | 2014-11-12 22:42:15 -0700 | [diff] [blame] | 98 | /** |
| 99 | * lpc_early_init() - set up LPC serial ports and other early things |
| 100 | * |
| 101 | * @blob: Device tree blob |
| 102 | * @node: Offset of LPC node |
| 103 | * @dev: PCH PCI device containing the LPC |
| 104 | * @return 0 if OK, -ve on error |
| 105 | */ |
| 106 | int lpc_early_init(const void *blob, int node, pci_dev_t dev); |
| 107 | |
| 108 | #endif |