| Simon Glass | dcfac35 | 2014-11-12 22:42:15 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2014 Google, Inc |
| 3 | * |
| 4 | * From Coreboot src/southbridge/intel/bd82x6x/pch.h |
| 5 | * |
| 6 | * Copyright (C) 2008-2009 coresystems GmbH |
| 7 | * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0 |
| 10 | */ |
| 11 | |
| 12 | #ifndef _ASM_ARCH_PCH_H |
| 13 | #define _ASM_ARCH_PCH_H |
| 14 | |
| 15 | #include <pci.h> |
| 16 | |
| 17 | /* PCI Configuration Space (D31:F0): LPC */ |
| 18 | #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0) |
| 19 | |
| 20 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 21 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| 22 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 23 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 24 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 25 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 26 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 27 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 28 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 29 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 30 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 31 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
| 32 | #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| 33 | #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| 34 | #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| 35 | #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
| 36 | #define LPC_GENX_DEC(x) (0x84 + 4 * (x)) |
| 37 | |
| 38 | /** |
| 39 | * lpc_early_init() - set up LPC serial ports and other early things |
| 40 | * |
| 41 | * @blob: Device tree blob |
| 42 | * @node: Offset of LPC node |
| 43 | * @dev: PCH PCI device containing the LPC |
| 44 | * @return 0 if OK, -ve on error |
| 45 | */ |
| 46 | int lpc_early_init(const void *blob, int node, pci_dev_t dev); |
| 47 | |
| 48 | #endif |