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Troy Kisky4b7c6022012-10-22 15:19:01 +00001/*
2 * watchdog.c - driver for i.mx on-chip watchdog
3 *
4 * Licensed under the GPL-2 or later.
5 */
6
7#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -07008#include <cpu_func.h>
Marek Vasutf7fc5c12019-06-09 03:46:22 +02009#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -070010#include <hang.h>
Troy Kisky4b7c6022012-10-22 15:19:01 +000011#include <asm/io.h>
Marek Vasutf7fc5c12019-06-09 03:46:22 +020012#include <wdt.h>
Troy Kisky4b7c6022012-10-22 15:19:01 +000013#include <watchdog.h>
14#include <asm/arch/imx-regs.h>
Xiaoliang Yanga6657ad2018-10-18 18:27:45 +080015#ifdef CONFIG_FSL_LSCH2
16#include <asm/arch/immap_lsch2.h>
17#endif
Fabio Estevamcd847ab2015-10-03 14:20:59 -030018#include <fsl_wdog.h>
Mo, Yuezhangc65adaa2020-07-01 09:15:28 +000019#include <div64.h>
20
21#define TIMEOUT_MAX 128000
22#define TIMEOUT_MIN 500
Troy Kisky4b7c6022012-10-22 15:19:01 +000023
Robert Hancockedc1d152019-08-06 11:05:30 -060024static void imx_watchdog_expire_now(struct watchdog_regs *wdog, bool ext_reset)
Troy Kisky4b7c6022012-10-22 15:19:01 +000025{
Robert Hancockedc1d152019-08-06 11:05:30 -060026 u16 wcr = WCR_WDE;
Marek Vasutf7fc5c12019-06-09 03:46:22 +020027
Robert Hancockedc1d152019-08-06 11:05:30 -060028 if (ext_reset)
29 wcr |= WCR_SRS; /* do not assert internal reset */
30 else
31 wcr |= WCR_WDA; /* do not assert external reset */
32
33 /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
34 writew(wcr, &wdog->wcr);
35 writew(wcr, &wdog->wcr);
36 writew(wcr, &wdog->wcr);
37
Marek Vasutf7fc5c12019-06-09 03:46:22 +020038 while (1) {
39 /*
Robert Hancockedc1d152019-08-06 11:05:30 -060040 * spin before reset
Marek Vasutf7fc5c12019-06-09 03:46:22 +020041 */
42 }
43}
44
45#if !defined(CONFIG_IMX_WATCHDOG) || \
46 (defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT))
Harald Seiler6f14d5f2020-12-15 16:47:52 +010047void __attribute__((weak)) reset_cpu(void)
Marek Vasutf7fc5c12019-06-09 03:46:22 +020048{
Troy Kisky4b7c6022012-10-22 15:19:01 +000049 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
50
Robert Hancockedc1d152019-08-06 11:05:30 -060051 imx_watchdog_expire_now(wdog, true);
Marek Vasutf7fc5c12019-06-09 03:46:22 +020052}
53#endif
54
55#if defined(CONFIG_IMX_WATCHDOG)
56static void imx_watchdog_reset(struct watchdog_regs *wdog)
57{
58#ifndef CONFIG_WATCHDOG_RESET_DISABLE
Troy Kisky4b7c6022012-10-22 15:19:01 +000059 writew(0x5555, &wdog->wsr);
60 writew(0xaaaa, &wdog->wsr);
Xiaoliang Yang09e92132018-10-18 18:27:46 +080061#endif /* CONFIG_WATCHDOG_RESET_DISABLE*/
Troy Kisky4b7c6022012-10-22 15:19:01 +000062}
63
Mo, Yuezhangc65adaa2020-07-01 09:15:28 +000064static void imx_watchdog_init(struct watchdog_regs *wdog, bool ext_reset,
65 u64 timeout)
Troy Kisky4b7c6022012-10-22 15:19:01 +000066{
Robert Hancockd00a0b12019-08-06 11:05:29 -060067 u16 wcr;
Troy Kisky4b7c6022012-10-22 15:19:01 +000068
69 /*
70 * The timer watchdog can be set between
Tom Rini0ab49a12023-01-10 11:19:44 -050071 * 0.5 and 128 Seconds.
Troy Kisky4b7c6022012-10-22 15:19:01 +000072 */
Mo, Yuezhangc65adaa2020-07-01 09:15:28 +000073 timeout = max_t(u64, timeout, TIMEOUT_MIN);
74 timeout = min_t(u64, timeout, TIMEOUT_MAX);
75 timeout = lldiv(timeout, 500) - 1;
76
Xiaoliang Yanga6657ad2018-10-18 18:27:45 +080077#ifdef CONFIG_FSL_LSCH2
Robert Hancockd00a0b12019-08-06 11:05:29 -060078 wcr = (WCR_WDA | WCR_SRS | WCR_WDE) << 8 | timeout;
Xiaoliang Yanga6657ad2018-10-18 18:27:45 +080079#else
Robert Hancockd00a0b12019-08-06 11:05:29 -060080 wcr = WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_SRS |
81 WCR_WDA | SET_WCR_WT(timeout);
82 if (ext_reset)
83 wcr |= WCR_WDT;
Xiaoliang Yanga6657ad2018-10-18 18:27:45 +080084#endif /* CONFIG_FSL_LSCH2*/
Robert Hancockd00a0b12019-08-06 11:05:29 -060085 writew(wcr, &wdog->wcr);
Marek Vasutf7fc5c12019-06-09 03:46:22 +020086 imx_watchdog_reset(wdog);
Troy Kisky4b7c6022012-10-22 15:19:01 +000087}
Troy Kisky4b7c6022012-10-22 15:19:01 +000088
Marek Vasutf7fc5c12019-06-09 03:46:22 +020089#if !CONFIG_IS_ENABLED(WDT)
90void hw_watchdog_reset(void)
Troy Kisky4b7c6022012-10-22 15:19:01 +000091{
92 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
93
Marek Vasutf7fc5c12019-06-09 03:46:22 +020094 imx_watchdog_reset(wdog);
95}
Peng Fan838cf7b2015-09-14 13:34:44 +080096
Marek Vasutf7fc5c12019-06-09 03:46:22 +020097void hw_watchdog_init(void)
98{
99 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
100
Mo, Yuezhangc65adaa2020-07-01 09:15:28 +0000101 imx_watchdog_init(wdog, true, CONFIG_WATCHDOG_TIMEOUT_MSECS);
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200102}
103#else
104struct imx_wdt_priv {
105 void __iomem *base;
Robert Hancockd00a0b12019-08-06 11:05:29 -0600106 bool ext_reset;
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200107};
108
109static int imx_wdt_reset(struct udevice *dev)
110{
111 struct imx_wdt_priv *priv = dev_get_priv(dev);
112
113 imx_watchdog_reset(priv->base);
114
115 return 0;
116}
117
118static int imx_wdt_expire_now(struct udevice *dev, ulong flags)
119{
120 struct imx_wdt_priv *priv = dev_get_priv(dev);
121
Robert Hancockedc1d152019-08-06 11:05:30 -0600122 imx_watchdog_expire_now(priv->base, priv->ext_reset);
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200123 hang();
124
125 return 0;
126}
127
128static int imx_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
129{
130 struct imx_wdt_priv *priv = dev_get_priv(dev);
131
Mo, Yuezhangc65adaa2020-07-01 09:15:28 +0000132 imx_watchdog_init(priv->base, priv->ext_reset, timeout);
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200133
134 return 0;
135}
136
137static int imx_wdt_probe(struct udevice *dev)
138{
139 struct imx_wdt_priv *priv = dev_get_priv(dev);
140
141 priv->base = dev_read_addr_ptr(dev);
142 if (!priv->base)
143 return -ENOENT;
144
Robert Hancockd00a0b12019-08-06 11:05:29 -0600145 priv->ext_reset = dev_read_bool(dev, "fsl,ext-reset-output");
146
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200147 return 0;
Troy Kisky4b7c6022012-10-22 15:19:01 +0000148}
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200149
150static const struct wdt_ops imx_wdt_ops = {
151 .start = imx_wdt_start,
152 .reset = imx_wdt_reset,
153 .expire_now = imx_wdt_expire_now,
154};
155
156static const struct udevice_id imx_wdt_ids[] = {
157 { .compatible = "fsl,imx21-wdt" },
158 {}
159};
160
161U_BOOT_DRIVER(imx_wdt) = {
162 .name = "imx_wdt",
163 .id = UCLASS_WDT,
164 .of_match = imx_wdt_ids,
165 .probe = imx_wdt_probe,
166 .ops = &imx_wdt_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700167 .priv_auto = sizeof(struct imx_wdt_priv),
Marek Vasutf7fc5c12019-06-09 03:46:22 +0200168 .flags = DM_FLAG_PRE_RELOC,
169};
170#endif
171#endif