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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekc8cf4712014-02-05 08:06:29 +01002/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simekc8cf4712014-02-05 08:06:29 +01007 */
8
9OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = 0x00000000;
15
16 . = ALIGN(4);
17 .text :
18 {
19 *(.__image_copy_start)
Masahiro Yamada22ea4152014-06-05 19:47:45 +090020 *(.vectors)
Michal Simekc8cf4712014-02-05 08:06:29 +010021 CPUDIR/start.o (.text*)
Alexander Graf94a10f22018-06-12 07:48:37 +020022 }
23
24 /* This needs to come before *(.text*) */
25 .__efi_runtime_start : {
26 *(.__efi_runtime_start)
27 }
28
29 .efi_runtime : {
30 *(.text.efi_runtime*)
31 *(.rodata.efi_runtime*)
32 *(.data.efi_runtime*)
33 }
34
35 .__efi_runtime_stop : {
36 *(.__efi_runtime_stop)
37 }
38
39 .text_rest :
40 {
Michal Simekc8cf4712014-02-05 08:06:29 +010041 *(.text*)
42 }
43
44 . = ALIGN(4);
45 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
46
47 . = ALIGN(4);
48 .data : {
49 *(.data*)
50 }
51
52 . = ALIGN(4);
53
54 . = .;
55
56 . = ALIGN(4);
Andrew Scull5a9095c2022-05-30 10:00:04 +000057 __u_boot_list : {
58 KEEP(*(SORT(__u_boot_list*)));
Michal Simekc8cf4712014-02-05 08:06:29 +010059 }
60
61 . = ALIGN(4);
62
Alexander Grafa56b5f12017-07-03 13:41:34 +020063 .efi_runtime_rel_start :
64 {
65 *(.__efi_runtime_rel_start)
66 }
67
68 .efi_runtime_rel : {
Alexander Graf94a10f22018-06-12 07:48:37 +020069 *(.rel*.efi_runtime)
70 *(.rel*.efi_runtime.*)
Alexander Grafa56b5f12017-07-03 13:41:34 +020071 }
72
73 .efi_runtime_rel_stop :
74 {
75 *(.__efi_runtime_rel_stop)
76 }
77
Michal Simek02d770a2022-08-31 11:28:59 +020078 . = ALIGN(8);
Michal Simekc8cf4712014-02-05 08:06:29 +010079 .image_copy_end :
80 {
81 *(.__image_copy_end)
82 }
83
84 .rel_dyn_start :
85 {
86 *(.__rel_dyn_start)
87 }
88
89 .rel.dyn : {
90 *(.rel*)
91 }
92
93 .rel_dyn_end :
94 {
95 *(.__rel_dyn_end)
96 }
97
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010098 .end :
99 {
100 *(.__end)
101 }
102
103 _image_binary_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +0100104
105/*
106 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
107 * __bss_base and __bss_limit are for linker only (overlay ordering)
108 */
109
110 .bss_start __rel_dyn_start (OVERLAY) : {
111 KEEP(*(.__bss_start));
112 __bss_base = .;
113 }
114
115 .bss __bss_base (OVERLAY) : {
116 *(.bss*)
Michal Simek02d770a2022-08-31 11:28:59 +0200117 . = ALIGN(8);
Michal Simekc8cf4712014-02-05 08:06:29 +0100118 __bss_limit = .;
119 }
120
121 .bss_end __bss_limit (OVERLAY) : {
122 KEEP(*(.__bss_end));
123 }
124
125 /*
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200126 * Zynq needs to discard these sections because the user
Michal Simekc8cf4712014-02-05 08:06:29 +0100127 * is expected to pass this image on to tools for boot.bin
128 * generation that require them to be dropped.
129 */
130 /DISCARD/ : { *(.dynsym) }
131 /DISCARD/ : { *(.dynbss*) }
132 /DISCARD/ : { *(.dynstr*) }
133 /DISCARD/ : { *(.dynamic*) }
134 /DISCARD/ : { *(.plt*) }
135 /DISCARD/ : { *(.interp*) }
136 /DISCARD/ : { *(.gnu*) }
137 /DISCARD/ : { *(.ARM.exidx*) }
138 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
139}