blob: 86559cb6aacec3f6caba3ee2ec98a2abbb63eb6e [file] [log] [blame]
Michal Simekc8cf4712014-02-05 08:06:29 +01001/*
2 * Copyright (c) 2004-2008 Texas Instruments
3 *
4 * (C) Copyright 2002
5 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
11OUTPUT_ARCH(arm)
12ENTRY(_start)
13SECTIONS
14{
15 . = 0x00000000;
16
17 . = ALIGN(4);
18 .text :
19 {
20 *(.__image_copy_start)
Masahiro Yamada22ea4152014-06-05 19:47:45 +090021 *(.vectors)
Michal Simekc8cf4712014-02-05 08:06:29 +010022 CPUDIR/start.o (.text*)
23 *(.text*)
24 }
25
26 . = ALIGN(4);
27 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
28
29 . = ALIGN(4);
30 .data : {
31 *(.data*)
32 }
33
34 . = ALIGN(4);
35
36 . = .;
37
38 . = ALIGN(4);
39 .u_boot_list : {
40 KEEP(*(SORT(.u_boot_list*)));
41 }
42
43 . = ALIGN(4);
44
Alexander Grafa56b5f12017-07-03 13:41:34 +020045 .__efi_runtime_start : {
46 *(.__efi_runtime_start)
47 }
48
49 .efi_runtime : {
50 *(efi_runtime_text)
51 *(efi_runtime_data)
52 }
53
54 .__efi_runtime_stop : {
55 *(.__efi_runtime_stop)
56 }
57
58 .efi_runtime_rel_start :
59 {
60 *(.__efi_runtime_rel_start)
61 }
62
63 .efi_runtime_rel : {
64 *(.relefi_runtime_text)
65 *(.relefi_runtime_data)
66 }
67
68 .efi_runtime_rel_stop :
69 {
70 *(.__efi_runtime_rel_stop)
71 }
72
73 . = ALIGN(4);
Michal Simekc8cf4712014-02-05 08:06:29 +010074 .image_copy_end :
75 {
76 *(.__image_copy_end)
77 }
78
79 .rel_dyn_start :
80 {
81 *(.__rel_dyn_start)
82 }
83
84 .rel.dyn : {
85 *(.rel*)
86 }
87
88 .rel_dyn_end :
89 {
90 *(.__rel_dyn_end)
91 }
92
Albert ARIBAUD9d25fa42014-02-22 17:53:42 +010093 .end :
94 {
95 *(.__end)
96 }
97
98 _image_binary_end = .;
Michal Simekc8cf4712014-02-05 08:06:29 +010099
100/*
101 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
102 * __bss_base and __bss_limit are for linker only (overlay ordering)
103 */
104
105 .bss_start __rel_dyn_start (OVERLAY) : {
106 KEEP(*(.__bss_start));
107 __bss_base = .;
108 }
109
110 .bss __bss_base (OVERLAY) : {
111 *(.bss*)
112 . = ALIGN(4);
113 __bss_limit = .;
114 }
115
116 .bss_end __bss_limit (OVERLAY) : {
117 KEEP(*(.__bss_end));
118 }
119
120 /*
Albert ARIBAUD9852cc62014-04-15 16:13:51 +0200121 * Zynq needs to discard these sections because the user
Michal Simekc8cf4712014-02-05 08:06:29 +0100122 * is expected to pass this image on to tools for boot.bin
123 * generation that require them to be dropped.
124 */
125 /DISCARD/ : { *(.dynsym) }
126 /DISCARD/ : { *(.dynbss*) }
127 /DISCARD/ : { *(.dynstr*) }
128 /DISCARD/ : { *(.dynamic*) }
129 /DISCARD/ : { *(.plt*) }
130 /DISCARD/ : { *(.interp*) }
131 /DISCARD/ : { *(.gnu*) }
132 /DISCARD/ : { *(.ARM.exidx*) }
133 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
134}