blob: 145bf3591ffb25b6ce62060c51ed9afd8d85b604 [file] [log] [blame]
Heiko Stuebnerfc367852019-07-16 22:18:21 +02001if ROCKCHIP_PX30
2
3config TARGET_EVB_PX30
4 bool "EVB_PX30"
Jagan Tekic6e50172020-10-28 19:03:43 +05305 help
6 This target config option used for below listed px30 boards.
7
8 EVB_PX30:
9 * EVB_PX30 is an evaluation board for Rockchip PX30.
Heiko Stuebnerfc367852019-07-16 22:18:21 +020010
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +020011config TARGET_ODROID_GO2
12 bool "ODROID_GO2"
13
Jagan Teki57a0a562020-10-28 19:03:45 +053014config TARGET_PX30_CORE
15 bool "Engicam PX30.Core"
16 help
17 PX30.Core EDIMM2.2:
18 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
19 * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam.
20 * PX30.Core needs to mount on top of EDIMM2.2 for creating complete
21 PX30.Core EDIMM2.2 Starter Kit.
22
Jagan Tekic7a3d132020-10-28 19:03:47 +053023 PX30.Core CTOUCH2:
24 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
25 * CTOUCH2.0 is a general purpose Carrier board with capacitive
26 touch interface support.
27 * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete
28 PX30.Core C.TOUCH Carrier board.
29
Jagan Teki19e0c952021-11-15 23:08:21 +053030 PX30.Core CTOUCH2-OF10:
31 * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.
32 * CTOUCH2.0 is a general purpose Carrier board with capacitive
33 touch interface support.
34 * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.
35 * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
36 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.
37
Heiko Stuebnerfc367852019-07-16 22:18:21 +020038config ROCKCHIP_BOOT_MODE_REG
39 default 0xff010200
40
41config SYS_SOC
42 default "px30"
43
44config SYS_MALLOC_F_LEN
45 default 0x400
46
Simon Glassf4d60392021-08-08 12:20:12 -060047config SPL_SERIAL
Heiko Stuebnerfc367852019-07-16 22:18:21 +020048 default y
49
50config TPL_LDSCRIPT
51 default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
52
53config TPL_TEXT_BASE
54 default 0xff0e1000
55
56config TPL_MAX_SIZE
57 default 10240
58
59config TPL_STACK
60 default 0xff0e4fff
61
Paul Kocialkowski7250b232019-11-28 15:27:51 +010062config DEBUG_UART_CHANNEL
63 int "Mux channel to use for debug UART2/UART3"
Heiko Stuebnerfc367852019-07-16 22:18:21 +020064 depends on DEBUG_UART_BOARD_INIT
65 default 0
66 help
Paul Kocialkowski7250b232019-11-28 15:27:51 +010067 UART2 and UART3 can use two different set of pins to route the output.
Heiko Stuebnerfc367852019-07-16 22:18:21 +020068 For using the UART for early debugging the route to use needs
69 to be declared (0 or 1).
70
Jagan Teki57a0a562020-10-28 19:03:45 +053071source "board/engicam/px30_core/Kconfig"
Heiko Stuebnera9ca71e2020-07-01 11:28:42 +020072source "board/hardkernel/odroid_go2/Kconfig"
Heiko Stuebnerfc367852019-07-16 22:18:21 +020073source "board/rockchip/evb_px30/Kconfig"
74
75endif