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Sumit Garge6a488b2022-07-12 12:42:11 +05301// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Clock drivers for Qualcomm QCS404
4 *
5 * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
6 */
7
Tom Riniabb9a042024-05-18 20:20:43 -06008#include <common.h>
Sumit Garge6a488b2022-07-12 12:42:11 +05309#include <clk-uclass.h>
10#include <dm.h>
11#include <errno.h>
12#include <asm/io.h>
13#include <linux/bitops.h>
Konrad Dybcio6c0b8442023-11-07 12:41:01 +000014#include <dt-bindings/clock/qcom,gcc-qcs404.h>
15
Caleb Connolly878b26a2023-11-07 12:40:59 +000016#include "clock-qcom.h"
Sumit Garge6a488b2022-07-12 12:42:11 +053017
Caleb Connolly10a0abb2023-11-07 12:41:03 +000018/* Clocks: (from CLK_CTL_BASE) */
19#define GPLL0_STATUS (0x21000)
20#define GPLL1_STATUS (0x20000)
21#define APCS_GPLL_ENA_VOTE (0x45000)
22#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
23
24/* BLSP1 AHB clock (root clock for BLSP) */
25#define BLSP1_AHB_CBCR 0x1008
26
27/* Uart clock control registers */
28#define BLSP1_UART2_BCR (0x3028)
29#define BLSP1_UART2_APPS_CBCR (0x302C)
30#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000031
32/* I2C controller clock control registerss */
33#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
34#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000035#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
36#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000037#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
38#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000039#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
40#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000041#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
42#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000043
44/* SD controller clock control registers */
45#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
Caleb Connollycbdad442024-04-03 14:07:40 +020046#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000047#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
48#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
49
50/* USB-3.0 controller clock control registers */
51#define SYS_NOC_USB3_CBCR (0x26014)
52#define USB30_BCR (0x39000)
53#define USB3PHY_BCR (0x39008)
54#define USB30_MASTER_CBCR (0x3900C)
55#define USB30_SLEEP_CBCR (0x39010)
56#define USB30_MOCK_UTMI_CBCR (0x39014)
57#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
58#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
59#define USB30_MASTER_CMD_RCGR (0x39028)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000060#define USB2A_PHY_SLEEP_CBCR (0x4102C)
61#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
62
63/* ETH controller clock control registers */
64#define ETH_PTP_CBCR (0x4e004)
65#define ETH_RGMII_CBCR (0x4e008)
66#define ETH_SLAVE_AHB_CBCR (0x4e00c)
67#define ETH_AXI_CBCR (0x4e010)
68#define EMAC_PTP_CMD_RCGR (0x4e014)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000069#define EMAC_CMD_RCGR (0x4e01c)
Caleb Connolly10a0abb2023-11-07 12:41:03 +000070
Sumit Garge6a488b2022-07-12 12:42:11 +053071
72/* GPLL0 clock control registers */
73#define GPLL0_STATUS_ACTIVE BIT(31)
74
Sumit Garge9e62342023-02-01 19:28:50 +053075#define CFG_CLK_SRC_GPLL1 BIT(8)
76#define GPLL1_STATUS_ACTIVE BIT(31)
77
Sumit Garge6a488b2022-07-12 12:42:11 +053078static struct vote_clk gcc_blsp1_ahb_clk = {
79 .cbcr_reg = BLSP1_AHB_CBCR,
80 .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
81 .vote_bit = BIT(10) | BIT(5) | BIT(4),
82};
83
Sumit Garge6a488b2022-07-12 12:42:11 +053084static struct pll_vote_clk gpll0_vote_clk = {
85 .status = GPLL0_STATUS,
86 .status_bit = GPLL0_STATUS_ACTIVE,
87 .ena_vote = APCS_GPLL_ENA_VOTE,
88 .vote_bit = BIT(0),
89};
90
Sumit Garge9e62342023-02-01 19:28:50 +053091static struct pll_vote_clk gpll1_vote_clk = {
92 .status = GPLL1_STATUS,
93 .status_bit = GPLL1_STATUS_ACTIVE,
94 .ena_vote = APCS_GPLL_ENA_VOTE,
95 .vote_bit = BIT(1),
96};
97
Caleb Connolly10a0abb2023-11-07 12:41:03 +000098static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
Sumit Garge6a488b2022-07-12 12:42:11 +053099{
100 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
101
102 switch (clk->id) {
103 case GCC_BLSP1_UART2_APPS_CLK:
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000104 /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
Caleb Connollycbdad442024-04-03 14:07:40 +0200105 clk_rcg_set_rate_mnd(priv->base, BLSP1_UART2_APPS_CMD_RCGR, 0, 12, 125,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000106 CFG_CLK_SRC_CXO, 16);
Sumit Garge6a488b2022-07-12 12:42:11 +0530107 clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000108 return 1843200;
Sumit Garge6a488b2022-07-12 12:42:11 +0530109 case GCC_SDCC1_APPS_CLK:
110 /* SDCC1: 200MHz */
Caleb Connollycbdad442024-04-03 14:07:40 +0200111 clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(0), 7, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000112 CFG_CLK_SRC_GPLL0, 8);
Sumit Garge6a488b2022-07-12 12:42:11 +0530113 clk_enable_gpll0(priv->base, &gpll0_vote_clk);
114 clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000115 return rate;
Sumit Garge9e62342023-02-01 19:28:50 +0530116 case GCC_ETH_RGMII_CLK:
117 if (rate == 250000000)
Caleb Connollycbdad442024-04-03 14:07:40 +0200118 clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000119 CFG_CLK_SRC_GPLL1, 8);
Sumit Garge9e62342023-02-01 19:28:50 +0530120 else if (rate == 125000000)
Caleb Connollycbdad442024-04-03 14:07:40 +0200121 clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 7, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000122 CFG_CLK_SRC_GPLL1, 8);
Sumit Garge9e62342023-02-01 19:28:50 +0530123 else if (rate == 50000000)
Caleb Connollycbdad442024-04-03 14:07:40 +0200124 clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 19, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000125 CFG_CLK_SRC_GPLL1, 8);
Sumit Garge9e62342023-02-01 19:28:50 +0530126 else if (rate == 5000000)
Caleb Connollycbdad442024-04-03 14:07:40 +0200127 clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 1, 50,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000128 CFG_CLK_SRC_GPLL1, 8);
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000129 return rate;
Sumit Garge6a488b2022-07-12 12:42:11 +0530130 }
131
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000132 /* There is a bug only seeming to affect this board where the MMC driver somehow calls
133 * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
134 * The only clock with ID 0 is the xo_board clock which should not be associated with
135 * this device...
136 */
137 log_debug("Unknown clock id %ld\n", clk->id);
Sumit Garge6a488b2022-07-12 12:42:11 +0530138 return 0;
139}
Sumit Garg1d1ca6e2022-08-04 19:57:14 +0530140
Caleb Connolly10a0abb2023-11-07 12:41:03 +0000141static int qcs404_clk_enable(struct clk *clk)
Sumit Garg1d1ca6e2022-08-04 19:57:14 +0530142{
Sumit Garg3018e522022-08-04 19:57:15 +0530143 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
144
145 switch (clk->id) {
146 case GCC_USB30_MASTER_CLK:
147 clk_enable_cbc(priv->base + USB30_MASTER_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200148 clk_rcg_set_rate_mnd(priv->base, USB30_MASTER_CMD_RCGR, 7, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000149 CFG_CLK_SRC_GPLL0, 8);
Sumit Garg3018e522022-08-04 19:57:15 +0530150 break;
151 case GCC_SYS_NOC_USB3_CLK:
152 clk_enable_cbc(priv->base + SYS_NOC_USB3_CBCR);
153 break;
154 case GCC_USB30_SLEEP_CLK:
155 clk_enable_cbc(priv->base + USB30_SLEEP_CBCR);
156 break;
157 case GCC_USB30_MOCK_UTMI_CLK:
158 clk_enable_cbc(priv->base + USB30_MOCK_UTMI_CBCR);
159 break;
160 case GCC_USB_HS_PHY_CFG_AHB_CLK:
161 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
162 break;
163 case GCC_USB2A_PHY_SLEEP_CLK:
164 clk_enable_cbc(priv->base + USB_HS_PHY_CFG_AHB_CBCR);
165 break;
Sumit Garge9e62342023-02-01 19:28:50 +0530166 case GCC_ETH_PTP_CLK:
167 /* SPEED_1000: freq -> 250MHz */
168 clk_enable_cbc(priv->base + ETH_PTP_CBCR);
169 clk_enable_gpll0(priv->base, &gpll1_vote_clk);
Caleb Connollycbdad442024-04-03 14:07:40 +0200170 clk_rcg_set_rate_mnd(priv->base, EMAC_PTP_CMD_RCGR, 3, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000171 CFG_CLK_SRC_GPLL1, 8);
Sumit Garge9e62342023-02-01 19:28:50 +0530172 break;
173 case GCC_ETH_RGMII_CLK:
174 /* SPEED_1000: freq -> 250MHz */
175 clk_enable_cbc(priv->base + ETH_RGMII_CBCR);
176 clk_enable_gpll0(priv->base, &gpll1_vote_clk);
Caleb Connollycbdad442024-04-03 14:07:40 +0200177 clk_rcg_set_rate_mnd(priv->base, EMAC_CMD_RCGR, 3, 0, 0,
Caleb Connollyfbacc672023-11-07 12:41:04 +0000178 CFG_CLK_SRC_GPLL1, 8);
Sumit Garge9e62342023-02-01 19:28:50 +0530179 break;
180 case GCC_ETH_SLAVE_AHB_CLK:
181 clk_enable_cbc(priv->base + ETH_SLAVE_AHB_CBCR);
182 break;
183 case GCC_ETH_AXI_CLK:
184 clk_enable_cbc(priv->base + ETH_AXI_CBCR);
185 break;
Sumit Garg89e0dff2023-02-13 10:19:09 +0530186 case GCC_BLSP1_AHB_CLK:
187 clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
188 break;
189 case GCC_BLSP1_QUP0_I2C_APPS_CLK:
190 clk_enable_cbc(priv->base + BLSP1_QUP0_I2C_APPS_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200191 clk_rcg_set_rate(priv->base, BLSP1_QUP0_I2C_APPS_CMD_RCGR, 0,
Sumit Garg89e0dff2023-02-13 10:19:09 +0530192 CFG_CLK_SRC_CXO);
193 break;
194 case GCC_BLSP1_QUP1_I2C_APPS_CLK:
195 clk_enable_cbc(priv->base + BLSP1_QUP1_I2C_APPS_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200196 clk_rcg_set_rate(priv->base, BLSP1_QUP1_I2C_APPS_CMD_RCGR, 0,
Sumit Garg89e0dff2023-02-13 10:19:09 +0530197 CFG_CLK_SRC_CXO);
198 break;
199 case GCC_BLSP1_QUP2_I2C_APPS_CLK:
200 clk_enable_cbc(priv->base + BLSP1_QUP2_I2C_APPS_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200201 clk_rcg_set_rate(priv->base, BLSP1_QUP2_I2C_APPS_CMD_RCGR, 0,
Sumit Garg89e0dff2023-02-13 10:19:09 +0530202 CFG_CLK_SRC_CXO);
203 break;
204 case GCC_BLSP1_QUP3_I2C_APPS_CLK:
205 clk_enable_cbc(priv->base + BLSP1_QUP3_I2C_APPS_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200206 clk_rcg_set_rate(priv->base, BLSP1_QUP3_I2C_APPS_CMD_RCGR, 0,
Sumit Garg89e0dff2023-02-13 10:19:09 +0530207 CFG_CLK_SRC_CXO);
208 break;
209 case GCC_BLSP1_QUP4_I2C_APPS_CLK:
210 clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
Caleb Connollycbdad442024-04-03 14:07:40 +0200211 clk_rcg_set_rate(priv->base, BLSP1_QUP4_I2C_APPS_CMD_RCGR, 0,
Sumit Garg89e0dff2023-02-13 10:19:09 +0530212 CFG_CLK_SRC_CXO);
213 break;
Caleb Connollyd718e3e2024-02-26 17:26:10 +0000214 case GCC_SDCC1_AHB_CLK:
215 clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
216 break;
Sumit Garg3018e522022-08-04 19:57:15 +0530217 default:
218 return 0;
219 }
220
Sumit Garg1d1ca6e2022-08-04 19:57:14 +0530221 return 0;
222}
Konrad Dybcio6c0b8442023-11-07 12:41:01 +0000223
224static const struct qcom_reset_map qcs404_gcc_resets[] = {
225 [GCC_GENI_IR_BCR] = { 0x0F000 },
226 [GCC_CDSP_RESTART] = { 0x18000 },
227 [GCC_USB_HS_BCR] = { 0x41000 },
228 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
229 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
230 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
231 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
232 [GCC_USB3_PHY_BCR] = { 0x39004 },
233 [GCC_USB_30_BCR] = { 0x39000 },
234 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
235 [GCC_PCIE_0_BCR] = { 0x3e000 },
236 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
237 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
238 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
239 [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
240 [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
241 [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
242 [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
243 [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
244 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
245 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
246 [GCC_EMAC_BCR] = { 0x4e000 },
247 [GCC_WDSP_RESTART] = {0x19000},
248};
249
Caleb Connolly10a0abb2023-11-07 12:41:03 +0000250static const struct msm_clk_data qcs404_clk_gcc_data = {
Konrad Dybcio6c0b8442023-11-07 12:41:01 +0000251 .resets = qcs404_gcc_resets,
252 .num_resets = ARRAY_SIZE(qcs404_gcc_resets),
Caleb Connolly10a0abb2023-11-07 12:41:03 +0000253 .enable = qcs404_clk_enable,
254 .set_rate = qcs404_clk_set_rate,
Konrad Dybcio6c0b8442023-11-07 12:41:01 +0000255};
256
257static const struct udevice_id gcc_qcs404_of_match[] = {
258 {
259 .compatible = "qcom,gcc-qcs404",
Caleb Connolly10a0abb2023-11-07 12:41:03 +0000260 .data = (ulong)&qcs404_clk_gcc_data
Konrad Dybcio6c0b8442023-11-07 12:41:01 +0000261 },
262 { }
263};
264
265U_BOOT_DRIVER(gcc_qcs404) = {
266 .name = "gcc_qcs404",
267 .id = UCLASS_NOP,
268 .of_match = gcc_qcs404_of_match,
269 .bind = qcom_cc_bind,
270 .flags = DM_FLAG_PRE_RELOC,
271};