clk/qcom: use function pointers for enable and set_rate
Currently, it isn't possible to build clock drivers for more than one
platform due to how the msm_enable() and msm_set_rate() callbacks are
implemented.
Extend qcom_clk_data to include function pointers for these and convert
all platforms to use them.
Previously, clock drivers relied on include/configs/<board.h> to include the
board specific sysmap header, however as most of the header contents are clock
driver related, import the contents directly into each clock driver and
remove the header. The only exception here is the dragonboard820c board file
which includes some pinctrl macros, those are also inlined.
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
[caleb: remove additional sysmap-sdm845.h mention]
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index 10ac360..9ad580b 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -15,6 +15,81 @@
#include "clock-qcom.h"
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x21000)
+#define GPLL1_STATUS (0x20000)
+#define APCS_GPLL_ENA_VOTE (0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR 0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR (0x3028)
+#define BLSP1_UART2_APPS_CBCR (0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR (0x3038)
+#define BLSP1_UART2_APPS_M (0x303C)
+#define BLSP1_UART2_APPS_N (0x3040)
+#define BLSP1_UART2_APPS_D (0x3044)
+
+/* I2C controller clock control registerss */
+#define BLSP1_QUP0_I2C_APPS_CBCR (0x6028)
+#define BLSP1_QUP0_I2C_APPS_CMD_RCGR (0x602C)
+#define BLSP1_QUP0_I2C_APPS_CFG_RCGR (0x6030)
+#define BLSP1_QUP1_I2C_APPS_CBCR (0x2008)
+#define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x200C)
+#define BLSP1_QUP1_I2C_APPS_CFG_RCGR (0x2010)
+#define BLSP1_QUP2_I2C_APPS_CBCR (0x3010)
+#define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x3000)
+#define BLSP1_QUP2_I2C_APPS_CFG_RCGR (0x3004)
+#define BLSP1_QUP3_I2C_APPS_CBCR (0x4020)
+#define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x4000)
+#define BLSP1_QUP3_I2C_APPS_CFG_RCGR (0x4004)
+#define BLSP1_QUP4_I2C_APPS_CBCR (0x5020)
+#define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x5000)
+#define BLSP1_QUP4_I2C_APPS_CFG_RCGR (0x5004)
+
+/* SD controller clock control registers */
+#define SDCC_BCR(n) (((n) * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n) (((n) * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n) (((n) * 0x1000) + 0x41008)
+#define SDCC_M(n) (((n) * 0x1000) + 0x4100C)
+#define SDCC_N(n) (((n) * 0x1000) + 0x41010)
+#define SDCC_D(n) (((n) * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n) (((n) * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n) (((n) * 0x1000) + 0x4101C)
+
+/* USB-3.0 controller clock control registers */
+#define SYS_NOC_USB3_CBCR (0x26014)
+#define USB30_BCR (0x39000)
+#define USB3PHY_BCR (0x39008)
+#define USB30_MASTER_CBCR (0x3900C)
+#define USB30_SLEEP_CBCR (0x39010)
+#define USB30_MOCK_UTMI_CBCR (0x39014)
+#define USB30_MOCK_UTMI_CMD_RCGR (0x3901C)
+#define USB30_MOCK_UTMI_CFG_RCGR (0x39020)
+#define USB30_MASTER_CMD_RCGR (0x39028)
+#define USB30_MASTER_CFG_RCGR (0x3902C)
+#define USB30_MASTER_M (0x39030)
+#define USB30_MASTER_N (0x39034)
+#define USB30_MASTER_D (0x39038)
+#define USB2A_PHY_SLEEP_CBCR (0x4102C)
+#define USB_HS_PHY_CFG_AHB_CBCR (0x41030)
+
+/* ETH controller clock control registers */
+#define ETH_PTP_CBCR (0x4e004)
+#define ETH_RGMII_CBCR (0x4e008)
+#define ETH_SLAVE_AHB_CBCR (0x4e00c)
+#define ETH_AXI_CBCR (0x4e010)
+#define EMAC_PTP_CMD_RCGR (0x4e014)
+#define EMAC_PTP_CFG_RCGR (0x4e018)
+#define EMAC_CMD_RCGR (0x4e01c)
+#define EMAC_CFG_RCGR (0x4e020)
+#define EMAC_M (0x4e024)
+#define EMAC_N (0x4e028)
+#define EMAC_D (0x4e02c)
+
/* GPLL0 clock control registers */
#define GPLL0_STATUS_ACTIVE BIT(31)
@@ -112,7 +187,7 @@
/* mnd_width = 0 */
};
-ulong msm_set_rate(struct clk *clk, ulong rate)
+static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -157,7 +232,7 @@
return 0;
}
-int msm_enable(struct clk *clk)
+static int qcs404_clk_enable(struct clk *clk)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -263,15 +338,17 @@
[GCC_WDSP_RESTART] = {0x19000},
};
-static const struct msm_clk_data qcs404_gcc_data = {
+static const struct msm_clk_data qcs404_clk_gcc_data = {
.resets = qcs404_gcc_resets,
.num_resets = ARRAY_SIZE(qcs404_gcc_resets),
+ .enable = qcs404_clk_enable,
+ .set_rate = qcs404_clk_set_rate,
};
static const struct udevice_id gcc_qcs404_of_match[] = {
{
.compatible = "qcom,gcc-qcs404",
- .data = (ulong)&qcs404_gcc_data
+ .data = (ulong)&qcs404_clk_gcc_data
},
{ }
};