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git01.mediatek.com / filogic / uboot / f188a4fa56085f888c3fa378cd84fadf95805290 / . / drivers / ddr / imx / imx9 / ddr_init.c
blob: 8b8ec7f8de3f6dd3ec1a102868ef71f80f9deee2 [file] [log] [blame]
Ye Lib2cfc422022-07-26 16:41:07 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
6#include <common.h>
7#include <errno.h>
8#include <log.h>
9#include <asm/io.h>
10#include <asm/arch/ddr.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/sys_proto.h>
13#include <linux/delay.h>
14
15void ddrphy_coldreset(void)
16{
17 /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
18 /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */
19 /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */
20
21 /* src_gen_dphy_apb_sw_rst_de_assert */
22 clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
23 /* src_gen_dphy_sw_rst_de_assert */
24 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
25 /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */
26 setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
27 mdelay(10);
28
29 /* src_gen_dphy_apb_sw_rst_assert */
30 setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
31 /* src_gen_dphy_sw_rst_assert */
32 setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
33 mdelay(10);
34 /* src_gen_dphy_PwrOKIn_sw_rst_assert */
35 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
36 mdelay(10);
37
38 /* src_gen_dphy_apb_sw_rst_de_assert */
39 clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
40 /* src_gen_dphy_sw_rst_de_assert() */
41 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
42}
43
44void check_ddrc_idle(void)
45{
46 u32 regval;
47
48 do {
49 regval = readl(REG_DDRDSR_2);
50 if (regval & BIT(31))
51 break;
52 } while (1);
53}
54
55void check_dfi_init_complete(void)
56{
57 u32 regval;
58
59 do {
60 regval = readl(REG_DDRDSR_2);
61 if (regval & BIT(2))
62 break;
63 } while (1);
64 setbits_le32(REG_DDRDSR_2, BIT(2));
65}
66
67void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
68{
69 int i = 0;
70
71 for (i = 0; i < num; i++) {
72 writel(ddrc_config->val, (ulong)ddrc_config->reg);
73 ddrc_config++;
74 }
75}
76
77void get_trained_CDD(u32 fsp)
78{
79}
80
81int ddr_init(struct dram_timing_info *dram_timing)
82{
83 unsigned int initial_drate;
84 int ret;
85 u32 regval;
86
87 debug("DDRINFO: start DRAM init\n");
88
89 /* reset ddrphy */
90 ddrphy_coldreset();
91
92 debug("DDRINFO: cfg clk\n");
93
94 initial_drate = dram_timing->fsp_msg[0].drate;
95 /* default to the frequency point 0 clock */
96 ddrphy_init_set_dfi_clk(initial_drate);
97
98 /*
99 * Start PHY initialization and training by
100 * accessing relevant PUB registers
101 */
102 debug("DDRINFO:ddrphy config start\n");
103
104 ret = ddr_cfg_phy(dram_timing);
105 if (ret)
106 return ret;
107
108 debug("DDRINFO: ddrphy config done\n");
109
110 /* rogram the ddrc registers */
111 debug("DDRINFO: ddrc config start\n");
112 ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
113 debug("DDRINFO: ddrc config done\n");
114
Ye Lif188a4f2022-07-26 16:41:08 +0800[diff] [blame^]115#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
116 writel(0x200000, REG_DDR_DEBUG_19);
117#endif
118
Ye Lib2cfc422022-07-26 16:41:07 +0800[diff] [blame]119 check_dfi_init_complete();
120
121 regval = readl(REG_DDR_SDRAM_CFG);
122 writel((regval | 0x80000000), REG_DDR_SDRAM_CFG);
123
124 check_ddrc_idle();
125
126 /* save the dram timing config into memory */
127 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
128
129 return 0;
130}
131
132ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr)
133{
134 u32 paddr_apb_qual;
135 u32 paddr_apb_unqual_dec_22_13;
136 u32 paddr_apb_unqual_dec_19_13;
137 u32 paddr_apb_unqual_dec_12_1;
138 u32 paddr_apb_unqual;
139 u32 paddr_apb_phy;
140
141 paddr_apb_qual = (paddr_apb_from_ctlr << 1);
142 paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13);
143 paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1);
144
145 switch (paddr_apb_unqual_dec_22_13) {
146 case 0x000:
147 paddr_apb_unqual_dec_19_13 = 0x00;
148 break;
149 case 0x001:
150 paddr_apb_unqual_dec_19_13 = 0x01;
151 break;
152 case 0x002:
153 paddr_apb_unqual_dec_19_13 = 0x02;
154 break;
155 case 0x003:
156 paddr_apb_unqual_dec_19_13 = 0x03;
157 break;
158 case 0x004:
159 paddr_apb_unqual_dec_19_13 = 0x04;
160 break;
161 case 0x005:
162 paddr_apb_unqual_dec_19_13 = 0x05;
163 break;
164 case 0x006:
165 paddr_apb_unqual_dec_19_13 = 0x06;
166 break;
167 case 0x007:
168 paddr_apb_unqual_dec_19_13 = 0x07;
169 break;
170 case 0x008:
171 paddr_apb_unqual_dec_19_13 = 0x08;
172 break;
173 case 0x009:
174 paddr_apb_unqual_dec_19_13 = 0x09;
175 break;
176 case 0x00a:
177 paddr_apb_unqual_dec_19_13 = 0x0a;
178 break;
179 case 0x00b:
180 paddr_apb_unqual_dec_19_13 = 0x0b;
181 break;
182 case 0x100:
183 paddr_apb_unqual_dec_19_13 = 0x0c;
184 break;
185 case 0x101:
186 paddr_apb_unqual_dec_19_13 = 0x0d;
187 break;
188 case 0x102:
189 paddr_apb_unqual_dec_19_13 = 0x0e;
190 break;
191 case 0x103:
192 paddr_apb_unqual_dec_19_13 = 0x0f;
193 break;
194 case 0x104:
195 paddr_apb_unqual_dec_19_13 = 0x10;
196 break;
197 case 0x105:
198 paddr_apb_unqual_dec_19_13 = 0x11;
199 break;
200 case 0x106:
201 paddr_apb_unqual_dec_19_13 = 0x12;
202 break;
203 case 0x107:
204 paddr_apb_unqual_dec_19_13 = 0x13;
205 break;
206 case 0x108:
207 paddr_apb_unqual_dec_19_13 = 0x14;
208 break;
209 case 0x109:
210 paddr_apb_unqual_dec_19_13 = 0x15;
211 break;
212 case 0x10a:
213 paddr_apb_unqual_dec_19_13 = 0x16;
214 break;
215 case 0x10b:
216 paddr_apb_unqual_dec_19_13 = 0x17;
217 break;
218 case 0x200:
219 paddr_apb_unqual_dec_19_13 = 0x18;
220 break;
221 case 0x201:
222 paddr_apb_unqual_dec_19_13 = 0x19;
223 break;
224 case 0x202:
225 paddr_apb_unqual_dec_19_13 = 0x1a;
226 break;
227 case 0x203:
228 paddr_apb_unqual_dec_19_13 = 0x1b;
229 break;
230 case 0x204:
231 paddr_apb_unqual_dec_19_13 = 0x1c;
232 break;
233 case 0x205:
234 paddr_apb_unqual_dec_19_13 = 0x1d;
235 break;
236 case 0x206:
237 paddr_apb_unqual_dec_19_13 = 0x1e;
238 break;
239 case 0x207:
240 paddr_apb_unqual_dec_19_13 = 0x1f;
241 break;
242 case 0x208:
243 paddr_apb_unqual_dec_19_13 = 0x20;
244 break;
245 case 0x209:
246 paddr_apb_unqual_dec_19_13 = 0x21;
247 break;
248 case 0x20a:
249 paddr_apb_unqual_dec_19_13 = 0x22;
250 break;
251 case 0x20b:
252 paddr_apb_unqual_dec_19_13 = 0x23;
253 break;
254 case 0x300:
255 paddr_apb_unqual_dec_19_13 = 0x24;
256 break;
257 case 0x301:
258 paddr_apb_unqual_dec_19_13 = 0x25;
259 break;
260 case 0x302:
261 paddr_apb_unqual_dec_19_13 = 0x26;
262 break;
263 case 0x303:
264 paddr_apb_unqual_dec_19_13 = 0x27;
265 break;
266 case 0x304:
267 paddr_apb_unqual_dec_19_13 = 0x28;
268 break;
269 case 0x305:
270 paddr_apb_unqual_dec_19_13 = 0x29;
271 break;
272 case 0x306:
273 paddr_apb_unqual_dec_19_13 = 0x2a;
274 break;
275 case 0x307:
276 paddr_apb_unqual_dec_19_13 = 0x2b;
277 break;
278 case 0x308:
279 paddr_apb_unqual_dec_19_13 = 0x2c;
280 break;
281 case 0x309:
282 paddr_apb_unqual_dec_19_13 = 0x2d;
283 break;
284 case 0x30a:
285 paddr_apb_unqual_dec_19_13 = 0x2e;
286 break;
287 case 0x30b:
288 paddr_apb_unqual_dec_19_13 = 0x2f;
289 break;
290 case 0x010:
291 paddr_apb_unqual_dec_19_13 = 0x30;
292 break;
293 case 0x011:
294 paddr_apb_unqual_dec_19_13 = 0x31;
295 break;
296 case 0x012:
297 paddr_apb_unqual_dec_19_13 = 0x32;
298 break;
299 case 0x013:
300 paddr_apb_unqual_dec_19_13 = 0x33;
301 break;
302 case 0x014:
303 paddr_apb_unqual_dec_19_13 = 0x34;
304 break;
305 case 0x015:
306 paddr_apb_unqual_dec_19_13 = 0x35;
307 break;
308 case 0x016:
309 paddr_apb_unqual_dec_19_13 = 0x36;
310 break;
311 case 0x017:
312 paddr_apb_unqual_dec_19_13 = 0x37;
313 break;
314 case 0x018:
315 paddr_apb_unqual_dec_19_13 = 0x38;
316 break;
317 case 0x019:
318 paddr_apb_unqual_dec_19_13 = 0x39;
319 break;
320 case 0x110:
321 paddr_apb_unqual_dec_19_13 = 0x3a;
322 break;
323 case 0x111:
324 paddr_apb_unqual_dec_19_13 = 0x3b;
325 break;
326 case 0x112:
327 paddr_apb_unqual_dec_19_13 = 0x3c;
328 break;
329 case 0x113:
330 paddr_apb_unqual_dec_19_13 = 0x3d;
331 break;
332 case 0x114:
333 paddr_apb_unqual_dec_19_13 = 0x3e;
334 break;
335 case 0x115:
336 paddr_apb_unqual_dec_19_13 = 0x3f;
337 break;
338 case 0x116:
339 paddr_apb_unqual_dec_19_13 = 0x40;
340 break;
341 case 0x117:
342 paddr_apb_unqual_dec_19_13 = 0x41;
343 break;
344 case 0x118:
345 paddr_apb_unqual_dec_19_13 = 0x42;
346 break;
347 case 0x119:
348 paddr_apb_unqual_dec_19_13 = 0x43;
349 break;
350 case 0x210:
351 paddr_apb_unqual_dec_19_13 = 0x44;
352 break;
353 case 0x211:
354 paddr_apb_unqual_dec_19_13 = 0x45;
355 break;
356 case 0x212:
357 paddr_apb_unqual_dec_19_13 = 0x46;
358 break;
359 case 0x213:
360 paddr_apb_unqual_dec_19_13 = 0x47;
361 break;
362 case 0x214:
363 paddr_apb_unqual_dec_19_13 = 0x48;
364 break;
365 case 0x215:
366 paddr_apb_unqual_dec_19_13 = 0x49;
367 break;
368 case 0x216:
369 paddr_apb_unqual_dec_19_13 = 0x4a;
370 break;
371 case 0x217:
372 paddr_apb_unqual_dec_19_13 = 0x4b;
373 break;
374 case 0x218:
375 paddr_apb_unqual_dec_19_13 = 0x4c;
376 break;
377 case 0x219:
378 paddr_apb_unqual_dec_19_13 = 0x4d;
379 break;
380 case 0x310:
381 paddr_apb_unqual_dec_19_13 = 0x4e;
382 break;
383 case 0x311:
384 paddr_apb_unqual_dec_19_13 = 0x4f;
385 break;
386 case 0x312:
387 paddr_apb_unqual_dec_19_13 = 0x50;
388 break;
389 case 0x313:
390 paddr_apb_unqual_dec_19_13 = 0x51;
391 break;
392 case 0x314:
393 paddr_apb_unqual_dec_19_13 = 0x52;
394 break;
395 case 0x315:
396 paddr_apb_unqual_dec_19_13 = 0x53;
397 break;
398 case 0x316:
399 paddr_apb_unqual_dec_19_13 = 0x54;
400 break;
401 case 0x317:
402 paddr_apb_unqual_dec_19_13 = 0x55;
403 break;
404 case 0x318:
405 paddr_apb_unqual_dec_19_13 = 0x56;
406 break;
407 case 0x319:
408 paddr_apb_unqual_dec_19_13 = 0x57;
409 break;
410 case 0x020:
411 paddr_apb_unqual_dec_19_13 = 0x58;
412 break;
413 case 0x120:
414 paddr_apb_unqual_dec_19_13 = 0x59;
415 break;
416 case 0x220:
417 paddr_apb_unqual_dec_19_13 = 0x5a;
418 break;
419 case 0x320:
420 paddr_apb_unqual_dec_19_13 = 0x5b;
421 break;
422 case 0x040:
423 paddr_apb_unqual_dec_19_13 = 0x5c;
424 break;
425 case 0x140:
426 paddr_apb_unqual_dec_19_13 = 0x5d;
427 break;
428 case 0x240:
429 paddr_apb_unqual_dec_19_13 = 0x5e;
430 break;
431 case 0x340:
432 paddr_apb_unqual_dec_19_13 = 0x5f;
433 break;
434 case 0x050:
435 paddr_apb_unqual_dec_19_13 = 0x60;
436 break;
437 case 0x051:
438 paddr_apb_unqual_dec_19_13 = 0x61;
439 break;
440 case 0x052:
441 paddr_apb_unqual_dec_19_13 = 0x62;
442 break;
443 case 0x053:
444 paddr_apb_unqual_dec_19_13 = 0x63;
445 break;
446 case 0x054:
447 paddr_apb_unqual_dec_19_13 = 0x64;
448 break;
449 case 0x055:
450 paddr_apb_unqual_dec_19_13 = 0x65;
451 break;
452 case 0x056:
453 paddr_apb_unqual_dec_19_13 = 0x66;
454 break;
455 case 0x057:
456 paddr_apb_unqual_dec_19_13 = 0x67;
457 break;
458 case 0x070:
459 paddr_apb_unqual_dec_19_13 = 0x68;
460 break;
461 case 0x090:
462 paddr_apb_unqual_dec_19_13 = 0x69;
463 break;
464 case 0x190:
465 paddr_apb_unqual_dec_19_13 = 0x6a;
466 break;
467 case 0x290:
468 paddr_apb_unqual_dec_19_13 = 0x6b;
469 break;
470 case 0x390:
471 paddr_apb_unqual_dec_19_13 = 0x6c;
472 break;
473 case 0x0c0:
474 paddr_apb_unqual_dec_19_13 = 0x6d;
475 break;
476 case 0x0d0:
477 paddr_apb_unqual_dec_19_13 = 0x6e;
478 break;
479 default:
480 paddr_apb_unqual_dec_19_13 = 0x00;
481 break;
482 }
483
484 paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1));
485
486 paddr_apb_phy = (paddr_apb_unqual << 1);
487
488 return paddr_apb_phy;
489}