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git01.mediatek.com / filogic / uboot / b2cfc42ccb088a20d6405ec418052632336afaa3 / . / drivers / ddr / imx / imx9 / ddr_init.c
blob: 16eac65105fa1cb95e5feef5be560de265b58093 [file] [log] [blame]
Ye Lib2cfc422022-07-26 16:41:07 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 */
5
6#include <common.h>
7#include <errno.h>
8#include <log.h>
9#include <asm/io.h>
10#include <asm/arch/ddr.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/sys_proto.h>
13#include <linux/delay.h>
14
15void ddrphy_coldreset(void)
16{
17 /* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
18 /* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */
19 /* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */
20
21 /* src_gen_dphy_apb_sw_rst_de_assert */
22 clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
23 /* src_gen_dphy_sw_rst_de_assert */
24 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
25 /* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */
26 setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
27 mdelay(10);
28
29 /* src_gen_dphy_apb_sw_rst_assert */
30 setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
31 /* src_gen_dphy_sw_rst_assert */
32 setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
33 mdelay(10);
34 /* src_gen_dphy_PwrOKIn_sw_rst_assert */
35 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
36 mdelay(10);
37
38 /* src_gen_dphy_apb_sw_rst_de_assert */
39 clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
40 /* src_gen_dphy_sw_rst_de_assert() */
41 clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
42}
43
44void check_ddrc_idle(void)
45{
46 u32 regval;
47
48 do {
49 regval = readl(REG_DDRDSR_2);
50 if (regval & BIT(31))
51 break;
52 } while (1);
53}
54
55void check_dfi_init_complete(void)
56{
57 u32 regval;
58
59 do {
60 regval = readl(REG_DDRDSR_2);
61 if (regval & BIT(2))
62 break;
63 } while (1);
64 setbits_le32(REG_DDRDSR_2, BIT(2));
65}
66
67void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
68{
69 int i = 0;
70
71 for (i = 0; i < num; i++) {
72 writel(ddrc_config->val, (ulong)ddrc_config->reg);
73 ddrc_config++;
74 }
75}
76
77void get_trained_CDD(u32 fsp)
78{
79}
80
81int ddr_init(struct dram_timing_info *dram_timing)
82{
83 unsigned int initial_drate;
84 int ret;
85 u32 regval;
86
87 debug("DDRINFO: start DRAM init\n");
88
89 /* reset ddrphy */
90 ddrphy_coldreset();
91
92 debug("DDRINFO: cfg clk\n");
93
94 initial_drate = dram_timing->fsp_msg[0].drate;
95 /* default to the frequency point 0 clock */
96 ddrphy_init_set_dfi_clk(initial_drate);
97
98 /*
99 * Start PHY initialization and training by
100 * accessing relevant PUB registers
101 */
102 debug("DDRINFO:ddrphy config start\n");
103
104 ret = ddr_cfg_phy(dram_timing);
105 if (ret)
106 return ret;
107
108 debug("DDRINFO: ddrphy config done\n");
109
110 /* rogram the ddrc registers */
111 debug("DDRINFO: ddrc config start\n");
112 ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
113 debug("DDRINFO: ddrc config done\n");
114
115 check_dfi_init_complete();
116
117 regval = readl(REG_DDR_SDRAM_CFG);
118 writel((regval | 0x80000000), REG_DDR_SDRAM_CFG);
119
120 check_ddrc_idle();
121
122 /* save the dram timing config into memory */
123 dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
124
125 return 0;
126}
127
128ulong ddrphy_addr_remap(u32 paddr_apb_from_ctlr)
129{
130 u32 paddr_apb_qual;
131 u32 paddr_apb_unqual_dec_22_13;
132 u32 paddr_apb_unqual_dec_19_13;
133 u32 paddr_apb_unqual_dec_12_1;
134 u32 paddr_apb_unqual;
135 u32 paddr_apb_phy;
136
137 paddr_apb_qual = (paddr_apb_from_ctlr << 1);
138 paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13);
139 paddr_apb_unqual_dec_12_1 = ((paddr_apb_qual & 0x1ffe) >> 1);
140
141 switch (paddr_apb_unqual_dec_22_13) {
142 case 0x000:
143 paddr_apb_unqual_dec_19_13 = 0x00;
144 break;
145 case 0x001:
146 paddr_apb_unqual_dec_19_13 = 0x01;
147 break;
148 case 0x002:
149 paddr_apb_unqual_dec_19_13 = 0x02;
150 break;
151 case 0x003:
152 paddr_apb_unqual_dec_19_13 = 0x03;
153 break;
154 case 0x004:
155 paddr_apb_unqual_dec_19_13 = 0x04;
156 break;
157 case 0x005:
158 paddr_apb_unqual_dec_19_13 = 0x05;
159 break;
160 case 0x006:
161 paddr_apb_unqual_dec_19_13 = 0x06;
162 break;
163 case 0x007:
164 paddr_apb_unqual_dec_19_13 = 0x07;
165 break;
166 case 0x008:
167 paddr_apb_unqual_dec_19_13 = 0x08;
168 break;
169 case 0x009:
170 paddr_apb_unqual_dec_19_13 = 0x09;
171 break;
172 case 0x00a:
173 paddr_apb_unqual_dec_19_13 = 0x0a;
174 break;
175 case 0x00b:
176 paddr_apb_unqual_dec_19_13 = 0x0b;
177 break;
178 case 0x100:
179 paddr_apb_unqual_dec_19_13 = 0x0c;
180 break;
181 case 0x101:
182 paddr_apb_unqual_dec_19_13 = 0x0d;
183 break;
184 case 0x102:
185 paddr_apb_unqual_dec_19_13 = 0x0e;
186 break;
187 case 0x103:
188 paddr_apb_unqual_dec_19_13 = 0x0f;
189 break;
190 case 0x104:
191 paddr_apb_unqual_dec_19_13 = 0x10;
192 break;
193 case 0x105:
194 paddr_apb_unqual_dec_19_13 = 0x11;
195 break;
196 case 0x106:
197 paddr_apb_unqual_dec_19_13 = 0x12;
198 break;
199 case 0x107:
200 paddr_apb_unqual_dec_19_13 = 0x13;
201 break;
202 case 0x108:
203 paddr_apb_unqual_dec_19_13 = 0x14;
204 break;
205 case 0x109:
206 paddr_apb_unqual_dec_19_13 = 0x15;
207 break;
208 case 0x10a:
209 paddr_apb_unqual_dec_19_13 = 0x16;
210 break;
211 case 0x10b:
212 paddr_apb_unqual_dec_19_13 = 0x17;
213 break;
214 case 0x200:
215 paddr_apb_unqual_dec_19_13 = 0x18;
216 break;
217 case 0x201:
218 paddr_apb_unqual_dec_19_13 = 0x19;
219 break;
220 case 0x202:
221 paddr_apb_unqual_dec_19_13 = 0x1a;
222 break;
223 case 0x203:
224 paddr_apb_unqual_dec_19_13 = 0x1b;
225 break;
226 case 0x204:
227 paddr_apb_unqual_dec_19_13 = 0x1c;
228 break;
229 case 0x205:
230 paddr_apb_unqual_dec_19_13 = 0x1d;
231 break;
232 case 0x206:
233 paddr_apb_unqual_dec_19_13 = 0x1e;
234 break;
235 case 0x207:
236 paddr_apb_unqual_dec_19_13 = 0x1f;
237 break;
238 case 0x208:
239 paddr_apb_unqual_dec_19_13 = 0x20;
240 break;
241 case 0x209:
242 paddr_apb_unqual_dec_19_13 = 0x21;
243 break;
244 case 0x20a:
245 paddr_apb_unqual_dec_19_13 = 0x22;
246 break;
247 case 0x20b:
248 paddr_apb_unqual_dec_19_13 = 0x23;
249 break;
250 case 0x300:
251 paddr_apb_unqual_dec_19_13 = 0x24;
252 break;
253 case 0x301:
254 paddr_apb_unqual_dec_19_13 = 0x25;
255 break;
256 case 0x302:
257 paddr_apb_unqual_dec_19_13 = 0x26;
258 break;
259 case 0x303:
260 paddr_apb_unqual_dec_19_13 = 0x27;
261 break;
262 case 0x304:
263 paddr_apb_unqual_dec_19_13 = 0x28;
264 break;
265 case 0x305:
266 paddr_apb_unqual_dec_19_13 = 0x29;
267 break;
268 case 0x306:
269 paddr_apb_unqual_dec_19_13 = 0x2a;
270 break;
271 case 0x307:
272 paddr_apb_unqual_dec_19_13 = 0x2b;
273 break;
274 case 0x308:
275 paddr_apb_unqual_dec_19_13 = 0x2c;
276 break;
277 case 0x309:
278 paddr_apb_unqual_dec_19_13 = 0x2d;
279 break;
280 case 0x30a:
281 paddr_apb_unqual_dec_19_13 = 0x2e;
282 break;
283 case 0x30b:
284 paddr_apb_unqual_dec_19_13 = 0x2f;
285 break;
286 case 0x010:
287 paddr_apb_unqual_dec_19_13 = 0x30;
288 break;
289 case 0x011:
290 paddr_apb_unqual_dec_19_13 = 0x31;
291 break;
292 case 0x012:
293 paddr_apb_unqual_dec_19_13 = 0x32;
294 break;
295 case 0x013:
296 paddr_apb_unqual_dec_19_13 = 0x33;
297 break;
298 case 0x014:
299 paddr_apb_unqual_dec_19_13 = 0x34;
300 break;
301 case 0x015:
302 paddr_apb_unqual_dec_19_13 = 0x35;
303 break;
304 case 0x016:
305 paddr_apb_unqual_dec_19_13 = 0x36;
306 break;
307 case 0x017:
308 paddr_apb_unqual_dec_19_13 = 0x37;
309 break;
310 case 0x018:
311 paddr_apb_unqual_dec_19_13 = 0x38;
312 break;
313 case 0x019:
314 paddr_apb_unqual_dec_19_13 = 0x39;
315 break;
316 case 0x110:
317 paddr_apb_unqual_dec_19_13 = 0x3a;
318 break;
319 case 0x111:
320 paddr_apb_unqual_dec_19_13 = 0x3b;
321 break;
322 case 0x112:
323 paddr_apb_unqual_dec_19_13 = 0x3c;
324 break;
325 case 0x113:
326 paddr_apb_unqual_dec_19_13 = 0x3d;
327 break;
328 case 0x114:
329 paddr_apb_unqual_dec_19_13 = 0x3e;
330 break;
331 case 0x115:
332 paddr_apb_unqual_dec_19_13 = 0x3f;
333 break;
334 case 0x116:
335 paddr_apb_unqual_dec_19_13 = 0x40;
336 break;
337 case 0x117:
338 paddr_apb_unqual_dec_19_13 = 0x41;
339 break;
340 case 0x118:
341 paddr_apb_unqual_dec_19_13 = 0x42;
342 break;
343 case 0x119:
344 paddr_apb_unqual_dec_19_13 = 0x43;
345 break;
346 case 0x210:
347 paddr_apb_unqual_dec_19_13 = 0x44;
348 break;
349 case 0x211:
350 paddr_apb_unqual_dec_19_13 = 0x45;
351 break;
352 case 0x212:
353 paddr_apb_unqual_dec_19_13 = 0x46;
354 break;
355 case 0x213:
356 paddr_apb_unqual_dec_19_13 = 0x47;
357 break;
358 case 0x214:
359 paddr_apb_unqual_dec_19_13 = 0x48;
360 break;
361 case 0x215:
362 paddr_apb_unqual_dec_19_13 = 0x49;
363 break;
364 case 0x216:
365 paddr_apb_unqual_dec_19_13 = 0x4a;
366 break;
367 case 0x217:
368 paddr_apb_unqual_dec_19_13 = 0x4b;
369 break;
370 case 0x218:
371 paddr_apb_unqual_dec_19_13 = 0x4c;
372 break;
373 case 0x219:
374 paddr_apb_unqual_dec_19_13 = 0x4d;
375 break;
376 case 0x310:
377 paddr_apb_unqual_dec_19_13 = 0x4e;
378 break;
379 case 0x311:
380 paddr_apb_unqual_dec_19_13 = 0x4f;
381 break;
382 case 0x312:
383 paddr_apb_unqual_dec_19_13 = 0x50;
384 break;
385 case 0x313:
386 paddr_apb_unqual_dec_19_13 = 0x51;
387 break;
388 case 0x314:
389 paddr_apb_unqual_dec_19_13 = 0x52;
390 break;
391 case 0x315:
392 paddr_apb_unqual_dec_19_13 = 0x53;
393 break;
394 case 0x316:
395 paddr_apb_unqual_dec_19_13 = 0x54;
396 break;
397 case 0x317:
398 paddr_apb_unqual_dec_19_13 = 0x55;
399 break;
400 case 0x318:
401 paddr_apb_unqual_dec_19_13 = 0x56;
402 break;
403 case 0x319:
404 paddr_apb_unqual_dec_19_13 = 0x57;
405 break;
406 case 0x020:
407 paddr_apb_unqual_dec_19_13 = 0x58;
408 break;
409 case 0x120:
410 paddr_apb_unqual_dec_19_13 = 0x59;
411 break;
412 case 0x220:
413 paddr_apb_unqual_dec_19_13 = 0x5a;
414 break;
415 case 0x320:
416 paddr_apb_unqual_dec_19_13 = 0x5b;
417 break;
418 case 0x040:
419 paddr_apb_unqual_dec_19_13 = 0x5c;
420 break;
421 case 0x140:
422 paddr_apb_unqual_dec_19_13 = 0x5d;
423 break;
424 case 0x240:
425 paddr_apb_unqual_dec_19_13 = 0x5e;
426 break;
427 case 0x340:
428 paddr_apb_unqual_dec_19_13 = 0x5f;
429 break;
430 case 0x050:
431 paddr_apb_unqual_dec_19_13 = 0x60;
432 break;
433 case 0x051:
434 paddr_apb_unqual_dec_19_13 = 0x61;
435 break;
436 case 0x052:
437 paddr_apb_unqual_dec_19_13 = 0x62;
438 break;
439 case 0x053:
440 paddr_apb_unqual_dec_19_13 = 0x63;
441 break;
442 case 0x054:
443 paddr_apb_unqual_dec_19_13 = 0x64;
444 break;
445 case 0x055:
446 paddr_apb_unqual_dec_19_13 = 0x65;
447 break;
448 case 0x056:
449 paddr_apb_unqual_dec_19_13 = 0x66;
450 break;
451 case 0x057:
452 paddr_apb_unqual_dec_19_13 = 0x67;
453 break;
454 case 0x070:
455 paddr_apb_unqual_dec_19_13 = 0x68;
456 break;
457 case 0x090:
458 paddr_apb_unqual_dec_19_13 = 0x69;
459 break;
460 case 0x190:
461 paddr_apb_unqual_dec_19_13 = 0x6a;
462 break;
463 case 0x290:
464 paddr_apb_unqual_dec_19_13 = 0x6b;
465 break;
466 case 0x390:
467 paddr_apb_unqual_dec_19_13 = 0x6c;
468 break;
469 case 0x0c0:
470 paddr_apb_unqual_dec_19_13 = 0x6d;
471 break;
472 case 0x0d0:
473 paddr_apb_unqual_dec_19_13 = 0x6e;
474 break;
475 default:
476 paddr_apb_unqual_dec_19_13 = 0x00;
477 break;
478 }
479
480 paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1));
481
482 paddr_apb_phy = (paddr_apb_unqual << 1);
483
484 return paddr_apb_phy;
485}