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Daniel Hellstrome045a4c2008-03-26 23:34:47 +01001/* Configuration header file for Gaisler Research AB's Template
2 * design (GPL Open Source SPARC/LEON3 96MHz) for Altera NIOS
3 * Development board Stratix II edition, with the FPGA device
4 * EP2S60.
5 *
6 * (C) Copyright 2003-2005
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * (C) Copyright 2008
10 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
11 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010013 */
14
15#ifndef __CONFIG_H__
16#define __CONFIG_H__
17
Francois Retief703d0242015-10-28 16:49:02 +020018#define CONFIG_DISPLAY_BOARDINFO
Francois Retiefb131cc52015-10-29 00:02:48 +020019
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010020/*
21 * High Level Configuration Options
22 * (easy to change)
23 */
24
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010025/* Altera NIOS Development board, Stratix II board */
Wolfgang Denka1be4762008-05-20 16:00:29 +020026#define CONFIG_GR_EP2S60 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010027
28/* CPU / AMBA BUS configuration */
Wolfgang Denka1be4762008-05-20 16:00:29 +020029#define CONFIG_SYS_CLK_FREQ 96000000 /* 96MHz */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010030
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010031/* Define this is the GR-2S60-MEZZ mezzanine is available and you
32 * want to use the USB and GRETH functionality of the board
33 */
34#undef GR_2S60_MEZZ
35
36#ifdef GR_2S60_MEZZ
37#define USE_GRETH 1
38#define USE_GRUSB 1
39#endif
40
41/*
42 * Serial console configuration
43 */
44#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010046
47/* Partitions */
48#define CONFIG_DOS_PARTITION
49#define CONFIG_MAC_PARTITION
50#define CONFIG_ISO_PARTITION
51
52/*
53 * Supported commands
54 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010055#define CONFIG_CMD_REGINFO
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010056#define CONFIG_CMD_DIAG
57#define CONFIG_CMD_IRQ
58
59/* USB support */
60#if USE_GRUSB
61#define CONFIG_USB_UHCI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010062/* Enable needed helper functions */
Jean-Christophe PLAGNIOL-VILLARD2a7a0312009-05-16 12:14:54 +020063#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010064#endif
65
66/*
67 * Autobooting
68 */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010069
70#define CONFIG_PREBOOT "echo;" \
71 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
72 "echo"
73
74#undef CONFIG_BOOTARGS
75
76#define CONFIG_EXTRA_ENV_SETTINGS \
77 "netdev=eth0\0" \
78 "nfsargs=setenv bootargs console=ttyS0,38400 root=/dev/nfs rw " \
79 "nfsroot=${serverip}:${rootpath}\0" \
80 "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram rw\0" \
81 "addip=setenv bootargs ${bootargs} " \
82 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
83 ":${hostname}:${netdev}:off panic=1\0" \
84 "flash_nfs=run nfsargs addip;" \
85 "bootm ${kernel_addr}\0" \
86 "flash_self=run ramargs addip;" \
87 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
88 "net_nfs=tftp 40000000 ${bootfile};run nfsargs addip;bootm\0" \
89 "scratch=40800000\0" \
Mike Frysingerc3c6bf12011-10-12 19:47:51 +000090 "getkernel=tftpboot $(scratch) $(bootfile)\0" \
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010091 "bootargs=console=ttyS0,38400 root=/dev/nfs rw nfsroot=192.168.0.20:/export/rootfs ip=192.168.0.207:192.168.0.20:192.168.0.1:255.255.255.0:ml401:eth0\0" \
92 ""
93
94#define CONFIG_NETMASK 255.255.255.0
95#define CONFIG_GATEWAYIP 192.168.0.1
96#define CONFIG_SERVERIP 192.168.0.20
97#define CONFIG_IPADDR 192.168.0.207
Joe Hershberger257ff782011-10-13 13:03:47 +000098#define CONFIG_ROOTPATH "/export/rootfs"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +010099#define CONFIG_HOSTNAME ml401
Joe Hershbergere4da2482011-10-13 13:03:48 +0000100#define CONFIG_BOOTFILE "/uImage"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100101
102#define CONFIG_BOOTCOMMAND "run flash_self"
103
104/* Memory MAP
105 *
106 * Flash:
107 * |--------------------------------|
108 * | 0x00000000 Text & Data & BSS | *
109 * | for Monitor | *
110 * | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~| *
111 * | UNUSED / Growth | * 256kb
112 * |--------------------------------|
113 * | 0x00050000 Base custom area | *
114 * | kernel / FS | *
115 * | | * Rest of Flash
116 * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
117 * | END-0x00008000 Environment | * 32kb
118 * |--------------------------------|
119 *
120 *
121 *
122 * Main Memory:
123 * |--------------------------------|
124 * | UNUSED / scratch area |
125 * | |
126 * | |
127 * | |
128 * | |
129 * |--------------------------------|
130 * | Monitor .Text / .DATA / .BSS | * 512kb
131 * | Relocated! | *
132 * |--------------------------------|
133 * | Monitor Malloc | * 128kb (contains relocated environment)
134 * |--------------------------------|
135 * | Monitor/kernel STACK | * 64kb
136 * |--------------------------------|
137 * | Page Table for MMU systems | * 2k
138 * |--------------------------------|
139 * | PROM Code accessed from Linux | * 6kb-128b
140 * |--------------------------------|
141 * | Global data (avail from kernel)| * 128b
142 * |--------------------------------|
143 *
144 */
145
146/*
147 * Flash configuration (8,16 or 32 MB)
148 * TEXT base always at 0xFFF00000
149 * ENV_ADDR always at 0xFFF40000
150 * FLASH_BASE at 0xFC000000 for 64 MB
151 * 0xFE000000 for 32 MB
152 * 0xFF000000 for 16 MB
153 * 0xFF800000 for 8 MB
154 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155/*#define CONFIG_SYS_NO_FLASH 1*/
156#define CONFIG_SYS_FLASH_BASE 0x00000000
157#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* FPGA Bit file is in top of FLASH, we only ues the bottom 4Mb */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100158
159#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
161#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100162
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200163#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
164#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
165#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
166#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
167#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100168
169/*** CFI CONFIG ***/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200171#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_CFI
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100173/* Bypass cache when reading regs from flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_CFI_BYPASS_READ
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100175/* Buffered writes (32byte/go) instead of single accesses */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100177
178/*
179 * Environment settings
180 */
Jean-Christophe PLAGNIOL-VILLARD68a87562008-09-10 22:48:00 +0200181/*#define CONFIG_ENV_IS_NOWHERE 1*/
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200182#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200183/* CONFIG_ENV_ADDR need to be at sector boundary */
184#define CONFIG_ENV_SIZE 0x8000
185#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_FLASH_SIZE-CONFIG_ENV_SECT_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100187#define CONFIG_ENV_OVERWRITE 1
188
189/*
190 * Memory map
191 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_SDRAM_BASE 0x40000000
193#define CONFIG_SYS_SDRAM_SIZE 0x02000000
194#define CONFIG_SYS_SDRAM_END (CONFIG_SYS_SDRAM_BASE+CONFIG_SYS_SDRAM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100195
196/* no SRAM available */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#undef CONFIG_SYS_SRAM_BASE
198#undef CONFIG_SYS_SRAM_SIZE
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_RAM_BASE CONFIG_SYS_SDRAM_BASE
201#define CONFIG_SYS_RAM_SIZE CONFIG_SYS_SDRAM_SIZE
202#define CONFIG_SYS_RAM_END CONFIG_SYS_SDRAM_END
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100203
Wolfgang Denk0191e472010-10-26 14:34:52 +0200204#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_END - GENERATED_GBL_DATA_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100205
Wolfgang Denk0191e472010-10-26 14:34:52 +0200206#define CONFIG_SYS_PROM_SIZE (8192-GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#define CONFIG_SYS_PROM_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET-CONFIG_SYS_PROM_SIZE)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100208
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_PROM_OFFSET-32)
210#define CONFIG_SYS_STACK_SIZE (0x10000-32)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100211
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200213#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
214# define CONFIG_SYS_RAMBOOT 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100215#endif
216
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200217#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
218#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100220
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_MALLOC_END (CONFIG_SYS_INIT_SP_OFFSET-CONFIG_SYS_STACK_SIZE)
222#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MALLOC_END-CONFIG_SYS_MALLOC_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100223
224/* relocated monitor area */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200225#define CONFIG_SYS_RELOC_MONITOR_MAX_END CONFIG_SYS_MALLOC_BASE
226#define CONFIG_SYS_RELOC_MONITOR_BASE (CONFIG_SYS_RELOC_MONITOR_MAX_END-CONFIG_SYS_MONITOR_LEN)
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100227
228/* make un relocated address from relocated address */
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200229#define UN_RELOC(address) (address-(CONFIG_SYS_RELOC_MONITOR_BASE-CONFIG_SYS_TEXT_BASE))
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100230
231/*
232 * Ethernet configuration uses on board SMC91C111, however if a mezzanine
233 * with a PHY is attached the GRETH can be used on this board.
234 * Define USE_GRETH in order to use the mezzanine provided PHY with the
235 * onchip GRETH network MAC, note that this is not supported by the
236 * template design.
237 */
238#ifndef USE_GRETH
239
240/* USE SMC91C111 MAC */
Ben Warren0fd6aae2009-10-04 22:37:03 -0700241#define CONFIG_SMC91111 1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100242#define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */
243#define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */
244#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
245/*#define CONFIG_SHOW_ACTIVITY*/
246#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
247
248#else
249
250/* USE GRETH Ethernet Driver */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100251#define CONFIG_GRETH 1
Masahiro Yamadacbafcdf2015-05-26 10:58:31 +0900252#endif
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100253
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100254#define CONFIG_PHY_ADDR 0x00
255
256/*
257 * Miscellaneous configurable options
258 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_LONGHELP /* undef to save memory */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100260#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100262#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100264#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200265#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
266#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
267#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100268
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200269#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
270#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100271
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200272#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100273
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100274/*-----------------------------------------------------------------------
275 * USB stuff
276 *-----------------------------------------------------------------------
277 */
278#define CONFIG_USB_CLOCK 0x0001BBBB
279#define CONFIG_USB_CONFIG 0x00005000
280
281/***** Gaisler GRLIB IP-Cores Config ********/
282
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#define CONFIG_SYS_GRLIB_SDRAM 0
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100284
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100285/* No SDRAM Configuration */
286#undef CONFIG_SYS_GRLIB_GAISLER_SDCTRL1
287
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100288/* See, GRLIB Docs (grip.pdf) on how to set up
289 * These the memory controller registers.
290 */
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100291#define CONFIG_SYS_GRLIB_ESA_MCTRL1
292#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG1 (0x10f800ff | (1<<11))
293#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG2 0x00000000
294#define CONFIG_SYS_GRLIB_ESA_MCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100295
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100296/* GRLIB FT-MCTRL configuration */
297#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1
298#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG1 (0x10f800ff | (1<<11))
299#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG2 0x00000000
300#define CONFIG_SYS_GRLIB_GAISLER_FTMCTRL1_CFG3 0x00000000
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100301
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100302/* DDR controller */
303#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1
304#define CONFIG_SYS_GRLIB_GAISLER_DDRSPA1_CTRL 0xa900830a
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100305
Daniel Hellstroma7da6a02010-01-25 09:56:08 +0100306/* no DDR2 Controller */
307#undef CONFIG_SYS_GRLIB_GAISLER_DDR2SPA1
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100308
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100309/* Identification string */
Francois Retief703d0242015-10-28 16:49:02 +0200310#define CONFIG_IDENT_STRING " Gaisler LEON3 EP2S60"
Daniel Hellstrome045a4c2008-03-26 23:34:47 +0100311
312/* default kernel command line */
313#define CONFIG_DEFAULT_KERNEL_COMMAND_LINE "console=ttyS0,38400\0\0"
314
315#endif /* __CONFIG_H */