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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +05302/*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on davinci_dvevm.h. Original Copyrights follow:
6 *
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +05308 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * Board
15 */
Lad, Prabhakarc618b612012-06-24 21:35:23 +000016/* check if direct NOR boot config is used */
17#ifndef CONFIG_DIRECT_NOR_BOOT
Stefano Babicfc850ab2010-11-11 15:38:02 +010018#define CONFIG_USE_SPIFLASH
Lad, Prabhakarc618b612012-06-24 21:35:23 +000019#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053020
21/*
Adam Ford5ff6c0a2017-09-17 20:43:46 -050022* Disable DM_* for SPL build and can be re-enabled after adding
23* DM support in SPL
24*/
25#ifdef CONFIG_SPL_BUILD
26#undef CONFIG_DM_SPI
27#undef CONFIG_DM_SPI_FLASH
28#undef CONFIG_DM_I2C
29#undef CONFIG_DM_I2C_COMPAT
30#endif
31/*
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053032 * SoC Configuration
33 */
Christian Riesch48c2d6d2012-02-02 00:44:39 +000034#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053035#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
36#define CONFIG_SYS_OSCIN_FREQ 24000000
37#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
38#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053039
Lad, Prabhakarc618b612012-06-24 21:35:23 +000040#ifdef CONFIG_DIRECT_NOR_BOOT
41#define CONFIG_ARCH_CPU_INIT
Lad, Prabhakarc618b612012-06-24 21:35:23 +000042#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
Lad, Prabhakarc618b612012-06-24 21:35:23 +000043#endif
44
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053045/*
46 * Memory Info
47 */
48#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053049#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
50#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Ben Gardiner7618f612010-08-23 09:08:15 -040051#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +053052
53/* memtest start addr */
54#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
55
56/* memtest will be run on 16MB */
57#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58
Christian Riesch63e341b2011-12-09 09:47:37 +000059#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
60 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
61 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
62 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
63 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
64 DAVINCI_SYSCFG_SUSPSRC_I2C)
65
66/*
67 * PLL configuration
68 */
Christian Riesch63e341b2011-12-09 09:47:37 +000069
70#define CONFIG_SYS_DA850_PLL0_PLLM 24
71#define CONFIG_SYS_DA850_PLL1_PLLM 21
72
73/*
74 * DDR2 memory configuration
75 */
76#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
77 DV_DDR_PHY_EXT_STRBEN | \
78 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
79
80#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
81 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
82 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
83 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
84 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
85 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
86 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
87 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
88
89/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
90#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
91
92#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
93 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
94 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \
95 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
96 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
97 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
98 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \
99 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
100 (0 << DV_DDR_SDTMR1_WTR_SHIFT))
101
102#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
103 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
104 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \
105 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
106 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
107 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
108 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
109 (0 << DV_DDR_SDTMR2_CKE_SHIFT))
110
111#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
112#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
113
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530114/*
115 * Serial Driver info
116 */
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500117
118#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DIRECT_NOR_BOOT)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530119#define CONFIG_SYS_NS16550_SERIAL
120#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
121#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500122#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530123#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530124
Stefano Babicfc850ab2010-11-11 15:38:02 +0100125#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500126#ifdef CONFIG_SPL_BUILD
127#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
Stefano Babicfc850ab2010-11-11 15:38:02 +0100128#define CONFIG_SF_DEFAULT_SPEED 30000000
129#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500130#endif
Stefano Babicfc850ab2010-11-11 15:38:02 +0100131
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000132#ifdef CONFIG_USE_SPIFLASH
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000133#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
Peter Howardb521c262014-12-17 12:14:36 +1100134#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
Lad, Prabhakara52e2602012-06-24 21:35:19 +0000135#endif
136
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530137/*
138 * I2C Configuration
139 */
Adam Ford66017122017-09-17 20:43:48 -0500140#ifndef CONFIG_SPL_BUILD
Sudhakar Rajashekhara5851e122010-11-18 09:59:37 -0500141#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
Adam Ford66017122017-09-17 20:43:48 -0500142#endif
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530143
144/*
Ben Gardiner314305c2010-10-14 17:26:25 -0400145 * Flash & Environment
146 */
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500147#ifdef CONFIG_NAND
Ben Gardiner314305c2010-10-14 17:26:25 -0400148#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
149#define CONFIG_ENV_SIZE (128 << 10)
150#define CONFIG_SYS_NAND_USE_FLASH_BBT
151#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
152#define CONFIG_SYS_NAND_PAGE_2K
153#define CONFIG_SYS_NAND_CS 3
154#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benardf7dafcf2013-04-22 05:55:00 +0000155#define CONFIG_SYS_NAND_MASK_CLE 0x10
156#define CONFIG_SYS_NAND_MASK_ALE 0x8
Ben Gardiner314305c2010-10-14 17:26:25 -0400157#undef CONFIG_SYS_NAND_HW_ECC
158#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Lad, Prabhakaref160a32012-06-24 21:35:22 +0000159#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
160#define CONFIG_SYS_NAND_5_ADDR_CYCLE
161#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
162#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
163#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
164#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
165#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
166#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
167#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
168 CONFIG_SYS_NAND_U_BOOT_SIZE - \
169 CONFIG_SYS_MALLOC_LEN - \
170 GENERATED_GBL_DATA_SIZE)
171#define CONFIG_SYS_NAND_ECCPOS { \
172 24, 25, 26, 27, 28, \
173 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
174 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
175 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
176 59, 60, 61, 62, 63 }
177#define CONFIG_SYS_NAND_PAGE_COUNT 64
178#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
179#define CONFIG_SYS_NAND_ECCSIZE 512
180#define CONFIG_SYS_NAND_ECCBYTES 10
181#define CONFIG_SYS_NAND_OOBSIZE 64
Scott Woodc352a0c2012-09-20 19:09:07 -0500182#define CONFIG_SPL_NAND_BASE
183#define CONFIG_SPL_NAND_DRIVERS
184#define CONFIG_SPL_NAND_ECC
Lad, Prabhakaref160a32012-06-24 21:35:22 +0000185#define CONFIG_SPL_NAND_LOAD
Ben Gardiner314305c2010-10-14 17:26:25 -0400186#endif
187
188/*
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400189 * Network & Ethernet Configuration
190 */
191#ifdef CONFIG_DRIVER_TI_EMAC
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400192#define CONFIG_BOOTP_DNS2
193#define CONFIG_BOOTP_SEND_HOSTNAME
194#define CONFIG_NET_RETRY_COUNT 10
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400195#endif
196
Nagabhushana Netagunte87539bf2011-09-03 22:18:32 -0400197#ifdef CONFIG_USE_NOR
Nagabhushana Netagunte87539bf2011-09-03 22:18:32 -0400198#define CONFIG_FLASH_CFI_DRIVER
199#define CONFIG_SYS_FLASH_CFI
200#define CONFIG_SYS_FLASH_PROTECTION
201#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
202#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
203#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
204#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
205#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
206#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
207#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
208 + 3)
209#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
210#endif
211
Stefano Babicfc850ab2010-11-11 15:38:02 +0100212#ifdef CONFIG_USE_SPIFLASH
Stefano Babicfc850ab2010-11-11 15:38:02 +0100213#define CONFIG_ENV_SIZE (64 << 10)
Peter Howardb521c262014-12-17 12:14:36 +1100214#define CONFIG_ENV_OFFSET (512 << 10)
Stefano Babicfc850ab2010-11-11 15:38:02 +0100215#define CONFIG_ENV_SECT_SIZE (64 << 10)
Adam Ford4c9c7232017-09-17 20:43:47 -0500216#ifdef CONFIG_SPL_BUILD
217#undef CONFIG_SPI_FLASH_MTD
218#endif
Stefano Babicfc850ab2010-11-11 15:38:02 +0100219#endif
220
Ben Gardiner4b9538a2010-10-14 17:26:29 -0400221/*
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530222 * U-Boot general configuration
223 */
224#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530225#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530226#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
227#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530228#define CONFIG_MX_CYCLIC
229
230/*
231 * Linux Information
232 */
Ben Gardiner14c2f7e2010-10-14 17:26:32 -0400233#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Nagabhushana Netagunte24d30962011-09-03 22:19:28 -0400234#define CONFIG_HWCONFIG /* enable hwconfig */
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530235#define CONFIG_CMDLINE_TAG
Sekhar Nori6e112202010-11-19 11:39:48 -0500236#define CONFIG_REVISION_TAG
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530237#define CONFIG_SETUP_MEMORY_TAGS
Adam Ford5ff6c0a2017-09-17 20:43:46 -0500238
239#define CONFIG_BOOTCOMMAND \
240 "run envboot; " \
241 "run mmcboot; "
242
243#define DEFAULT_LINUX_BOOT_ENV \
244 "loadaddr=0xc0700000\0" \
245 "fdtaddr=0xc0600000\0" \
246 "scriptaddr=0xc0600000\0"
247
248#include <environment/ti/mmc.h>
249
250#define CONFIG_EXTRA_ENV_SETTINGS \
251 DEFAULT_LINUX_BOOT_ENV \
252 DEFAULT_MMC_TI_ARGS \
253 "bootpart=0:2\0" \
254 "bootdir=/boot\0" \
255 "bootfile=zImage\0" \
256 "fdtfile=da850-evm.dtb\0" \
257 "boot_fdt=yes\0" \
258 "boot_fit=0\0" \
259 "console=ttyS2,115200n8\0" \
260 "hwconfig=dsp:wake=yes"
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530261
Hadli, Manjunath0dfccbe2012-02-06 00:30:44 +0000262#ifdef CONFIG_CMD_BDI
263#define CONFIG_CLOCKS
264#endif
265
Adam Fordfc3ad5b2018-07-10 06:47:33 -0500266#if !defined(CONFIG_NAND) && \
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530267 !defined(CONFIG_USE_NOR) && \
268 !defined(CONFIG_USE_SPIFLASH)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530269#define CONFIG_ENV_SIZE (16 << 10)
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530270#endif
271
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000272#ifndef CONFIG_DIRECT_NOR_BOOT
Christian Riesch63e341b2011-12-09 09:47:37 +0000273/* defines for SPL */
Tom Rini12938582012-08-14 12:27:13 -0700274#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
275 CONFIG_SYS_MALLOC_LEN)
276#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Christian Riesch63e341b2011-12-09 09:47:37 +0000277#define CONFIG_SPL_STACK 0x8001ff00
278#define CONFIG_SPL_TEXT_BASE 0x80000000
Albert ARIBAUDa02e3cc2013-04-12 05:14:32 +0000279#define CONFIG_SPL_MAX_FOOTPRINT 32768
Christian Riesch40aad402014-05-07 10:16:28 +0200280#define CONFIG_SPL_PAD_TO 32768
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000281#endif
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +0000282
283/* Load U-Boot Image From MMC */
Lad, Prabhakar8dc6df82012-06-24 21:35:20 +0000284
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200285/* additions for new relocation code, must added to all boards */
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200286#define CONFIG_SYS_SDRAM_BASE 0xc0000000
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000287
288#ifdef CONFIG_DIRECT_NOR_BOOT
289#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
290#else
Heiko Schocher0e2412a2010-09-17 13:10:42 +0200291#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
Wolfgang Denk0191e472010-10-26 14:34:52 +0200292 GENERATED_GBL_DATA_SIZE)
Lad, Prabhakarc618b612012-06-24 21:35:23 +0000293#endif /* CONFIG_DIRECT_NOR_BOOT */
Simon Glassce3574f2017-05-17 08:23:09 -0600294
295#include <asm/arch/hardware.h>
296
Sudhakar Rajashekhara68921812010-06-10 15:18:15 +0530297#endif /* __CONFIG_H */