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git01.mediatek.com / filogic / uboot / f0826d7306e447d0c4e93c61182bc7a860c1fe7e / . / arch / arm / dts / rk3328.dtsi
blob: 6095a124b09c03a56918f4a481849fc73e0a2a72 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]2/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]4 */
5
6#include <dt-bindings/clock/rk3328-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11
12/ {
13 compatible = "rockchip,rk3328";
14
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
Kever Yang73518912017-05-18 16:05:20 +0800[diff] [blame]27 mmc0 = &emmc;
28 mmc1 = &sdmmc;
29 mmc2 = &sdmmc_ext;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]30 };
31
32 cpus {
33 #address-cells = <2>;
34 #size-cells = <0>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a53", "arm,armv8";
39 reg = <0x0 0x0>;
40 enable-method = "psci";
41// clocks = <&cru ARMCLK>;
42 operating-points-v2 = <&cpu0_opp_table>;
43 };
44 cpu1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a53", "arm,armv8";
47 reg = <0x0 0x1>;
48 enable-method = "psci";
49 };
50 cpu2: cpu@2 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0x0 0x2>;
54 enable-method = "psci";
55 };
56 cpu3: cpu@3 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53", "arm,armv8";
59 reg = <0x0 0x3>;
60 enable-method = "psci";
61 };
62 };
63
64 cpu0_opp_table: opp_table0 {
65 compatible = "operating-points-v2";
66 opp-shared;
67
68 opp@408000000 {
69 opp-hz = /bits/ 64 <408000000>;
70 opp-microvolt = <950000>;
71 clock-latency-ns = <40000>;
72 opp-suspend;
73 };
74 opp@600000000 {
75 opp-hz = /bits/ 64 <600000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
78 };
79 opp@816000000 {
80 opp-hz = /bits/ 64 <816000000>;
81 opp-microvolt = <1000000>;
82 clock-latency-ns = <40000>;
83 };
84 opp@1008000000 {
85 opp-hz = /bits/ 64 <1008000000>;
86 opp-microvolt = <1100000>;
87 clock-latency-ns = <40000>;
88 };
89 opp@1200000000 {
90 opp-hz = /bits/ 64 <1200000000>;
91 opp-microvolt = <1225000>;
92 clock-latency-ns = <40000>;
93 };
94 opp@1296000000 {
95 opp-hz = /bits/ 64 <1296000000>;
96 opp-microvolt = <1300000>;
97 clock-latency-ns = <40000>;
98 };
99 };
100
101 arm-pmu {
102 compatible = "arm,cortex-a53-pmu";
103 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
108 };
109
110 psci {
111 compatible = "arm,psci-1.0";
112 method = "smc";
113 };
114
115 timer {
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
121 };
122
123 xin24m: xin24m {
124 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 clock-frequency = <24000000>;
127 clock-output-names = "xin24m";
128 };
129
130 i2s0: i2s@ff000000 {
131 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
132 reg = <0x0 0xff000000 0x0 0x1000>;
133 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
135 clock-names = "i2s_clk", "i2s_hclk";
136 dmas = <&dmac 11>, <&dmac 12>;
137 #dma-cells = <2>;
138 dma-names = "tx", "rx";
139 status = "disabled";
140 };
141
142 i2s1: i2s@ff010000 {
143 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
144 reg = <0x0 0xff010000 0x0 0x1000>;
145 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
147 clock-names = "i2s_clk", "i2s_hclk";
148 dmas = <&dmac 14>, <&dmac 15>;
149 #dma-cells = <2>;
150 dma-names = "tx", "rx";
151 status = "disabled";
152 };
153
154 i2s2: i2s@ff020000 {
155 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
156 reg = <0x0 0xff020000 0x0 0x1000>;
157 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
159 clock-names = "i2s_clk", "i2s_hclk";
160 dmas = <&dmac 0>, <&dmac 1>;
161 #dma-cells = <2>;
162 dma-names = "tx", "rx";
163 pinctrl-names = "default", "sleep";
164 pinctrl-0 = <&i2s2m0_mclk
165 &i2s2m0_sclk
166 &i2s2m0_lrcktx
167 &i2s2m0_lrckrx
168 &i2s2m0_sdo
169 &i2s2m0_sdi>;
170 pinctrl-1 = <&i2s2m0_sleep>;
171 status = "disabled";
172 };
173
174 spdif: spdif@ff030000 {
175 compatible = "rockchip,rk3328-spdif";
176 reg = <0x0 0xff030000 0x0 0x1000>;
177 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
179 clock-names = "mclk", "hclk";
180 dmas = <&dmac 10>;
181 #dma-cells = <1>;
182 dma-names = "tx";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdifm2_tx>;
185 status = "disabled";
186 };
187
188 grf: syscon@ff100000 {
Kever Yangf1a14462017-06-23 16:11:09 +0800[diff] [blame]189 u-boot,dm-pre-reloc;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]190 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
191 reg = <0x0 0xff100000 0x0 0x1000>;
192 #address-cells = <1>;
193 #size-cells = <1>;
194
195 io_domains: io-domains {
196 compatible = "rockchip,rk3328-io-voltage-domain";
197 status = "disabled";
198 };
199 };
200
201 uart0: serial@ff110000 {
202 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
203 reg = <0x0 0xff110000 0x0 0x100>;
204 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
206 clock-names = "baudclk", "apb_pclk";
207 reg-shift = <2>;
208 reg-io-width = <4>;
209 dmas = <&dmac 2>, <&dmac 3>;
210 #dma-cells = <2>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
213 status = "disabled";
214 };
215
216 uart1: serial@ff120000 {
217 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
218 reg = <0x0 0xff120000 0x0 0x100>;
219 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
221 clock-names = "sclk_uart", "pclk_uart";
222 reg-shift = <2>;
223 reg-io-width = <4>;
224 dmas = <&dmac 4>, <&dmac 5>;
225 #dma-cells = <2>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
228 status = "disabled";
229 };
230
231 uart2: serial@ff130000 {
232 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
233 reg = <0x0 0xff130000 0x0 0x100>;
234 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
236 clock-names = "baudclk", "apb_pclk";
237 clock-frequency = <24000000>;
238 reg-shift = <2>;
239 reg-io-width = <4>;
240 dmas = <&dmac 6>, <&dmac 7>;
241 #dma-cells = <2>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&uart2m1_xfer>;
244 status = "disabled";
245 };
246
247 pmu: power-management@ff140000 {
248 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
249 reg = <0x0 0xff140000 0x0 0x1000>;
250 };
251
252 i2c0: i2c@ff150000 {
253 compatible = "rockchip,rk3328-i2c";
254 reg = <0x0 0xff150000 0x0 0x1000>;
255 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
256 #address-cells = <1>;
257 #size-cells = <0>;
258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
259 clock-names = "i2c", "pclk";
260 pinctrl-names = "default";
261 pinctrl-0 = <&i2c0_xfer>;
262 status = "disabled";
263 };
264
265 i2c1: i2c@ff160000 {
266 compatible = "rockchip,rk3328-i2c";
267 reg = <0x0 0xff160000 0x0 0x1000>;
268 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
272 clock-names = "i2c", "pclk";
273 pinctrl-names = "default";
274 pinctrl-0 = <&i2c1_xfer>;
275 status = "disabled";
276 };
277
278 i2c2: i2c@ff170000 {
279 compatible = "rockchip,rk3328-i2c";
280 reg = <0x0 0xff170000 0x0 0x1000>;
281 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
285 clock-names = "i2c", "pclk";
286 pinctrl-names = "default";
287 pinctrl-0 = <&i2c2_xfer>;
288 status = "disabled";
289 };
290
291 i2c3: i2c@ff180000 {
292 compatible = "rockchip,rk3328-i2c";
293 reg = <0x0 0xff180000 0x0 0x1000>;
294 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
298 clock-names = "i2c", "pclk";
299 pinctrl-names = "default";
300 pinctrl-0 = <&i2c3_xfer>;
301 status = "disabled";
302 };
303
304 spi0: spi@ff190000 {
305 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
306 reg = <0x0 0xff190000 0x0 0x1000>;
307 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
311 clock-names = "spiclk", "apb_pclk";
312 dmas = <&dmac 8>, <&dmac 9>;
313 #dma-cells = <2>;
314 dma-names = "tx", "rx";
315 pinctrl-names = "default";
316 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
317 status = "disabled";
318 };
319
320 wdt: watchdog@ff1a0000 {
321 compatible = "snps,dw-wdt";
322 reg = <0x0 0xff1a0000 0x0 0x100>;
323 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
324 status = "disabled";
325 };
326
327 amba {
328 compatible = "simple-bus";
329 #address-cells = <2>;
330 #size-cells = <2>;
331 ranges;
332
333 dmac: dmac@ff1f0000 {
334 compatible = "arm,pl330", "arm,primecell";
335 reg = <0x0 0xff1f0000 0x0 0x4000>;
336 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru ACLK_DMAC>;
339 clock-names = "apb_pclk";
340 #dma-cells = <1>;
341 };
342 };
343
344 saradc: saradc@ff280000 {
345 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
346 reg = <0x0 0xff280000 0x0 0x100>;
347 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
348 #io-channel-cells = <1>;
349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
350 clock-names = "saradc", "apb_pclk";
351 resets = <&cru SRST_SARADC_P>;
352 reset-names = "saradc-apb";
353 status = "disabled";
354 };
355
Kever Yangf1a14462017-06-23 16:11:09 +0800[diff] [blame]356 dmc: dmc@ff400000 {
357 u-boot,dm-pre-reloc;
358 compatible = "rockchip,rk3328-dmc", "syscon";
359 reg = <0x0 0xff400000 0x0 0x1000>;
360 };
361
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]362 cru: clock-controller@ff440000 {
363 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
364 reg = <0x0 0xff440000 0x0 0x1000>;
365 rockchip,grf = <&grf>;
366 #clock-cells = <1>;
367 #reset-cells = <1>;
368 assigned-clocks =
369 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
370 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
371 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
372 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
373 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
374 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
375 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
376 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
377 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
378 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
379 <&cru SCLK_WIFI>, <&cru ARMCLK>,
380 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
381 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
382 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
383 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
384 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
385 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
390 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
391 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
392 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
393 assigned-clock-parents =
394 <&cru HDMIPHY>, <&cru PLL_APLL>,
395 <&cru PLL_GPLL>, <&xin24m>,
396 <&xin24m>, <&xin24m>;
397 assigned-clock-rates =
398 <0>, <61440000>,
399 <0>, <24000000>,
400 <24000000>, <24000000>,
401 <15000000>, <15000000>,
402 <100000000>, <100000000>,
403 <100000000>, <100000000>,
404 <50000000>, <100000000>,
405 <100000000>, <100000000>,
406 <50000000>, <50000000>,
407 <50000000>, <50000000>,
408 <24000000>, <600000000>,
409 <491520000>, <1200000000>,
410 <150000000>, <75000000>,
411 <75000000>, <150000000>,
412 <75000000>, <75000000>,
413 <300000000>, <100000000>,
414 <300000000>, <200000000>,
415 <400000000>, <500000000>,
416 <200000000>, <300000000>,
417 <300000000>, <250000000>,
418 <200000000>, <100000000>,
419 <24000000>, <100000000>,
420 <150000000>, <50000000>,
421 <32768>, <32768>;
422 };
423
424 sdmmc: rksdmmc@ff500000 {
425 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
426 reg = <0x0 0xff500000 0x0 0x4000>;
Kever Yang08401422017-06-14 16:31:45 +0800[diff] [blame]427 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]428 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
429 clock-names = "biu", "ciu";
430 fifo-depth = <0x100>;
431 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
432 status = "disabled";
433 };
434
435 sdio: dwmmc@ff510000 {
436 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
437 reg = <0x0 0xff510000 0x0 0x4000>;
Kever Yang08401422017-06-14 16:31:45 +0800[diff] [blame]438 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]439 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
440 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
441 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
442 fifo-depth = <0x100>;
443 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
444 status = "disabled";
445 };
446
447 emmc: rksdmmc@ff520000 {
448 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
449 reg = <0x0 0xff520000 0x0 0x4000>;
Kever Yang08401422017-06-14 16:31:45 +0800[diff] [blame]450 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]451 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
452 clock-names = "biu", "ciu";
453 fifo-depth = <0x100>;
454 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
455 status = "disabled";
456 };
457
David Wu29b0bfd2018-01-13 14:03:56 +0800[diff] [blame]458 gmac2io: ethernet@ff540000 {
459 compatible = "rockchip,rk3328-gmac";
460 reg = <0x0 0xff540000 0x0 0x10000>;
461 rockchip,grf = <&grf>;
462 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "macirq";
464 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
465 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
466 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
467 <&cru PCLK_MAC2IO>;
468 clock-names = "stmmaceth", "mac_clk_rx",
469 "mac_clk_tx", "clk_mac_ref",
470 "clk_mac_refout", "aclk_mac",
471 "pclk_mac";
472 resets = <&cru SRST_GMAC2IO_A>;
473 reset-names = "stmmaceth";
474 status = "disabled";
475 };
476
Meng Dongyang4fd2d8f2017-05-17 18:21:46 +0800[diff] [blame]477 usb_host0_ehci: usb@ff5c0000 {
478 compatible = "generic-ehci";
479 reg = <0x0 0xff5c0000 0x0 0x10000>;
480 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
481 status = "disabled";
482 };
483
484 usb_host0_ohci: usb@ff5d0000 {
485 compatible = "generic-ohci";
486 reg = <0x0 0xff5d0000 0x0 0x10000>;
487 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
488 status = "disabled";
489 };
490
Meng Dongyangc27dcf92017-06-28 19:22:45 +0800[diff] [blame]491 usb20_otg: usb@ff580000 {
492 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
493 "snps,dwc2";
494 reg = <0x0 0xff580000 0x0 0x40000>;
495 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
496 hnp-srp-disable;
497 dr_mode = "otg";
498 status = "disabled";
499 };
500
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]501 sdmmc_ext: rksdmmc@ff5f0000 {
502 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
503 reg = <0x0 0xff5f0000 0x0 0x4000>;
Kever Yang08401422017-06-14 16:31:45 +0800[diff] [blame]504 max-frequency = <150000000>;
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]505 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
506 clock-names = "biu", "ciu";
507 fifo-depth = <0x100>;
508 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
509 status = "disabled";
510 };
511
Meng Dongyang820d1122017-05-17 18:25:28 +0800[diff] [blame]512 usb_host0_xhci: usb@ff600000 {
513 compatible = "rockchip,rk3328-xhci";
514 reg = <0x0 0xff600000 0x0 0x100000>;
515 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
516 snps,dis-enblslpm-quirk;
517 snps,phyif-utmi-bits = <16>;
518 snps,dis-u2-freeclk-exists-quirk;
519 snps,dis-u2-susphy-quirk;
520 status = "disabled";
521 };
522
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]523 gic: interrupt-controller@ffb70000 {
524 compatible = "arm,gic-400";
525 #interrupt-cells = <3>;
526 #address-cells = <0>;
527 interrupt-controller;
528 reg = <0x0 0xff811000 0 0x1000>,
529 <0x0 0xff812000 0 0x2000>,
530 <0x0 0xff814000 0 0x2000>,
531 <0x0 0xff816000 0 0x2000>;
532 interrupts = <GIC_PPI 9
533 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
534 };
535
536 pinctrl: pinctrl {
537 compatible = "rockchip,rk3328-pinctrl";
538 rockchip,grf = <&grf>;
539 #address-cells = <2>;
540 #size-cells = <2>;
541 ranges;
542
543 gpio0: gpio0@ff210000 {
544 compatible = "rockchip,gpio-bank";
545 reg = <0x0 0xff210000 0x0 0x100>;
546 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&cru PCLK_GPIO0>;
548
549 gpio-controller;
550 #gpio-cells = <2>;
551
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 };
555
556 gpio1: gpio1@ff220000 {
557 compatible = "rockchip,gpio-bank";
558 reg = <0x0 0xff220000 0x0 0x100>;
559 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&cru PCLK_GPIO1>;
561
562 gpio-controller;
563 #gpio-cells = <2>;
564
565 interrupt-controller;
566 #interrupt-cells = <2>;
567 };
568
569 gpio2: gpio2@ff230000 {
570 compatible = "rockchip,gpio-bank";
571 reg = <0x0 0xff230000 0x0 0x100>;
572 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&cru PCLK_GPIO2>;
574
575 gpio-controller;
576 #gpio-cells = <2>;
577
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 };
581
582 gpio3: gpio3@ff240000 {
583 compatible = "rockchip,gpio-bank";
584 reg = <0x0 0xff240000 0x0 0x100>;
585 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
586 clocks = <&cru PCLK_GPIO3>;
587
588 gpio-controller;
589 #gpio-cells = <2>;
590
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 };
594
595 pcfg_pull_up: pcfg-pull-up {
596 bias-pull-up;
597 };
598
599 pcfg_pull_down: pcfg-pull-down {
600 bias-pull-down;
601 };
602
603 pcfg_pull_none: pcfg-pull-none {
604 bias-disable;
605 };
606
607 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
608 bias-disable;
609 drive-strength = <2>;
610 };
611
612 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
613 bias-pull-up;
614 drive-strength = <2>;
615 };
616
617 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
618 bias-pull-up;
619 drive-strength = <4>;
620 };
621
622 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
623 bias-disable;
624 drive-strength = <4>;
625 };
626
627 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
628 bias-pull-down;
629 drive-strength = <4>;
630 };
631
632 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
633 bias-disable;
634 drive-strength = <8>;
635 };
636
637 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
638 bias-pull-up;
639 drive-strength = <8>;
640 };
641
642 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
643 bias-disable;
644 drive-strength = <12>;
645 };
646
647 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
648 bias-pull-up;
649 drive-strength = <12>;
650 };
651
652 pcfg_output_high: pcfg-output-high {
653 output-high;
654 };
655
656 pcfg_output_low: pcfg-output-low {
657 output-low;
658 };
659
660 pcfg_input_high: pcfg-input-high {
661 bias-pull-up;
662 input-enable;
663 };
664
665 pcfg_input: pcfg-input {
666 input-enable;
667 };
668
669 i2c0 {
670 i2c0_xfer: i2c0-xfer {
671 rockchip,pins =
672 <2 24 RK_FUNC_1 &pcfg_pull_none>,
673 <2 25 RK_FUNC_1 &pcfg_pull_none>;
674 };
675 };
676
677 i2c1 {
678 i2c1_xfer: i2c1-xfer {
679 rockchip,pins =
680 <2 4 RK_FUNC_2 &pcfg_pull_none>,
681 <2 5 RK_FUNC_2 &pcfg_pull_none>;
682 };
683 };
684
685 i2c2 {
686 i2c2_xfer: i2c2-xfer {
687 rockchip,pins =
688 <2 13 RK_FUNC_1 &pcfg_pull_none>,
689 <2 14 RK_FUNC_1 &pcfg_pull_none>;
690 };
691 };
692
693 i2c3 {
694 i2c3_xfer: i2c3-xfer {
695 rockchip,pins =
696 <0 5 RK_FUNC_2 &pcfg_pull_none>,
697 <0 6 RK_FUNC_2 &pcfg_pull_none>;
698 };
699 i2c3_gpio: i2c3-gpio {
700 rockchip,pins =
701 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
702 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
703 };
704 };
705
706 hdmi_i2c {
707 hdmii2c_xfer: hdmii2c-xfer {
708 rockchip,pins =
709 <0 5 RK_FUNC_1 &pcfg_pull_none>,
710 <0 6 RK_FUNC_1 &pcfg_pull_none>;
711 };
712 };
713
714 uart0 {
715 uart0_xfer: uart0-xfer {
716 rockchip,pins =
717 <1 9 RK_FUNC_1 &pcfg_pull_up>,
718 <1 8 RK_FUNC_1 &pcfg_pull_none>;
719 };
720
721 uart0_cts: uart0-cts {
722 rockchip,pins =
723 <1 11 RK_FUNC_1 &pcfg_pull_none>;
724 };
725
726 uart0_rts: uart0-rts {
727 rockchip,pins =
728 <1 10 RK_FUNC_1 &pcfg_pull_none>;
729 };
730
731 uart0_rts_gpio: uart0-rts-gpio {
732 rockchip,pins =
733 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
734 };
735 };
736
737 uart1 {
738 uart1_xfer: uart1-xfer {
739 rockchip,pins =
740 <3 4 RK_FUNC_4 &pcfg_pull_up>,
741 <3 6 RK_FUNC_4 &pcfg_pull_none>;
742 };
743
744 uart1_cts: uart1-cts {
745 rockchip,pins =
746 <3 7 RK_FUNC_4 &pcfg_pull_none>;
747 };
748
749 uart1_rts: uart1-rts {
750 rockchip,pins =
751 <3 5 RK_FUNC_4 &pcfg_pull_none>;
752 };
753
754 uart1_rts_gpio: uart1-rts-gpio {
755 rockchip,pins =
756 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
757 };
758 };
759
760 uart2-0 {
761 uart2m0_xfer: uart2m0-xfer {
762 rockchip,pins =
763 <1 0 RK_FUNC_2 &pcfg_pull_up>,
764 <1 1 RK_FUNC_2 &pcfg_pull_none>;
765 };
766 };
767
768 uart2-1 {
769 uart2m1_xfer: uart2m1-xfer {
770 rockchip,pins =
771 <2 0 RK_FUNC_1 &pcfg_pull_up>,
772 <2 1 RK_FUNC_1 &pcfg_pull_none>;
773 };
774 };
775
776 spi0-0 {
777 spi0m0_clk: spi0m0-clk {
778 rockchip,pins =
779 <2 8 RK_FUNC_1 &pcfg_pull_up>;
780 };
781
782 spi0m0_cs0: spi0m0-cs0 {
783 rockchip,pins =
784 <2 11 RK_FUNC_1 &pcfg_pull_up>;
785 };
786
787 spi0m0_tx: spi0m0-tx {
788 rockchip,pins =
789 <2 9 RK_FUNC_1 &pcfg_pull_up>;
790 };
791
792 spi0m0_rx: spi0m0-rx {
793 rockchip,pins =
794 <2 10 RK_FUNC_1 &pcfg_pull_up>;
795 };
796
797 spi0m0_cs1: spi0m0-cs1 {
798 rockchip,pins =
799 <2 12 RK_FUNC_1 &pcfg_pull_up>;
800 };
801 };
802
803 spi0-1 {
804 spi0m1_clk: spi0m1-clk {
805 rockchip,pins =
806 <3 23 RK_FUNC_2 &pcfg_pull_up>;
807 };
808
809 spi0m1_cs0: spi0m1-cs0 {
810 rockchip,pins =
811 <3 26 RK_FUNC_2 &pcfg_pull_up>;
812 };
813
814 spi0m1_tx: spi0m1-tx {
815 rockchip,pins =
816 <3 25 RK_FUNC_2 &pcfg_pull_up>;
817 };
818
819 spi0m1_rx: spi0m1-rx {
820 rockchip,pins =
821 <3 24 RK_FUNC_2 &pcfg_pull_up>;
822 };
823
824 spi0m1_cs1: spi0m1-cs1 {
825 rockchip,pins =
826 <3 27 RK_FUNC_2 &pcfg_pull_up>;
827 };
828 };
829
830 spi0-2 {
831 spi0m2_clk: spi0m2-clk {
832 rockchip,pins =
833 <3 0 RK_FUNC_4 &pcfg_pull_up>;
834 };
835
836 spi0m2_cs0: spi0m2-cs0 {
837 rockchip,pins =
838 <3 8 RK_FUNC_3 &pcfg_pull_up>;
839 };
840
841 spi0m2_tx: spi0m2-tx {
842 rockchip,pins =
843 <3 1 RK_FUNC_4 &pcfg_pull_up>;
844 };
845
846 spi0m2_rx: spi0m2-rx {
847 rockchip,pins =
848 <3 2 RK_FUNC_4 &pcfg_pull_up>;
849 };
850 };
851
852 i2s1 {
853 i2s1_mclk: i2s1-mclk {
854 rockchip,pins =
855 <2 15 RK_FUNC_1 &pcfg_pull_none>;
856 };
857
858 i2s1_sclk: i2s1-sclk {
859 rockchip,pins =
860 <2 18 RK_FUNC_1 &pcfg_pull_none>;
861 };
862
863 i2s1_lrckrx: i2s1-lrckrx {
864 rockchip,pins =
865 <2 16 RK_FUNC_1 &pcfg_pull_none>;
866 };
867
868 i2s1_lrcktx: i2s1-lrcktx {
869 rockchip,pins =
870 <2 17 RK_FUNC_1 &pcfg_pull_none>;
871 };
872
873 i2s1_sdi: i2s1-sdi {
874 rockchip,pins =
875 <2 19 RK_FUNC_1 &pcfg_pull_none>;
876 };
877
878 i2s1_sdo: i2s1-sdo {
879 rockchip,pins =
880 <2 23 RK_FUNC_1 &pcfg_pull_none>;
881 };
882
883 i2s1_sdio1: i2s1-sdio1 {
884 rockchip,pins =
885 <2 20 RK_FUNC_1 &pcfg_pull_none>;
886 };
887
888 i2s1_sdio2: i2s1-sdio2 {
889 rockchip,pins =
890 <2 21 RK_FUNC_1 &pcfg_pull_none>;
891 };
892
893 i2s1_sdio3: i2s1-sdio3 {
894 rockchip,pins =
895 <2 22 RK_FUNC_1 &pcfg_pull_none>;
896 };
897
898 i2s1_sleep: i2s1-sleep {
899 rockchip,pins =
900 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
901 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
902 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
903 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
904 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
905 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
906 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
907 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
908 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
909 };
910 };
911
912 i2s2-0 {
913 i2s2m0_mclk: i2s2m0-mclk {
914 rockchip,pins =
915 <1 21 RK_FUNC_1 &pcfg_pull_none>;
916 };
917
918 i2s2m0_sclk: i2s2m0-sclk {
919 rockchip,pins =
920 <1 22 RK_FUNC_1 &pcfg_pull_none>;
921 };
922
923 i2s2m0_lrckrx: i2s2m0-lrckrx {
924 rockchip,pins =
925 <1 26 RK_FUNC_1 &pcfg_pull_none>;
926 };
927
928 i2s2m0_lrcktx: i2s2m0-lrcktx {
929 rockchip,pins =
930 <1 23 RK_FUNC_1 &pcfg_pull_none>;
931 };
932
933 i2s2m0_sdi: i2s2m0-sdi {
934 rockchip,pins =
935 <1 24 RK_FUNC_1 &pcfg_pull_none>;
936 };
937
938 i2s2m0_sdo: i2s2m0-sdo {
939 rockchip,pins =
940 <1 25 RK_FUNC_1 &pcfg_pull_none>;
941 };
942
943 i2s2m0_sleep: i2s2m0-sleep {
944 rockchip,pins =
945 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
946 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
947 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
948 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
949 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
950 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
951 };
952 };
953
954 i2s2-1 {
955 i2s2m1_mclk: i2s2m1-mclk {
956 rockchip,pins =
957 <1 21 RK_FUNC_1 &pcfg_pull_none>;
958 };
959
960 i2s2m1_sclk: i2s2m1-sclk {
961 rockchip,pins =
962 <3 0 RK_FUNC_6 &pcfg_pull_none>;
963 };
964
965 i2s2m1_lrckrx: i2sm1-lrckrx {
966 rockchip,pins =
967 <3 8 RK_FUNC_6 &pcfg_pull_none>;
968 };
969
970 i2s2m1_lrcktx: i2s2m1-lrcktx {
971 rockchip,pins =
972 <3 8 RK_FUNC_4 &pcfg_pull_none>;
973 };
974
975 i2s2m1_sdi: i2s2m1-sdi {
976 rockchip,pins =
977 <3 2 RK_FUNC_6 &pcfg_pull_none>;
978 };
979
980 i2s2m1_sdo: i2s2m1-sdo {
981 rockchip,pins =
982 <3 1 RK_FUNC_6 &pcfg_pull_none>;
983 };
984
985 i2s2m1_sleep: i2s2m1-sleep {
986 rockchip,pins =
987 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
988 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
989 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
990 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
991 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
992 };
993 };
994
995 spdif-0 {
996 spdifm0_tx: spdifm0-tx {
997 rockchip,pins =
998 <0 27 RK_FUNC_1 &pcfg_pull_none>;
999 };
1000 };
1001
1002 spdif-1 {
1003 spdifm1_tx: spdifm1-tx {
1004 rockchip,pins =
1005 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1006 };
1007 };
1008
1009 spdif-2 {
1010 spdifm2_tx: spdifm2-tx {
1011 rockchip,pins =
1012 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1013 };
1014 };
1015
1016 sdmmc0-0 {
1017 sdmmc0m0_pwren: sdmmc0m0-pwren {
1018 rockchip,pins =
1019 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1020 };
1021
1022 sdmmc0m0_gpio: sdmmc0m0-gpio {
1023 rockchip,pins =
1024 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1025 };
1026 };
1027
1028 sdmmc0-1 {
1029 sdmmc0m1_pwren: sdmmc0m1-pwren {
1030 rockchip,pins =
1031 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1032 };
1033
1034 sdmmc0m1_gpio: sdmmc0m1-gpio {
1035 rockchip,pins =
1036 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1037 };
1038 };
1039
1040 sdmmc0 {
1041 sdmmc0_clk: sdmmc0-clk {
1042 rockchip,pins =
1043 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1044 };
1045
1046 sdmmc0_cmd: sdmmc0-cmd {
1047 rockchip,pins =
1048 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1049 };
1050
1051 sdmmc0_dectn: sdmmc0-dectn {
1052 rockchip,pins =
1053 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1054 };
1055
1056 sdmmc0_wrprt: sdmmc0-wrprt {
1057 rockchip,pins =
1058 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1059 };
1060
1061 sdmmc0_bus1: sdmmc0-bus1 {
1062 rockchip,pins =
1063 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1064 };
1065
1066 sdmmc0_bus4: sdmmc0-bus4 {
1067 rockchip,pins =
1068 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1069 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1070 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1071 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1072 };
1073
1074 sdmmc0_gpio: sdmmc0-gpio {
1075 rockchip,pins =
1076 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1077 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1078 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1079 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1080 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1081 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1082 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1083 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1084 };
1085 };
1086
1087 sdmmc0ext {
1088 sdmmc0ext_clk: sdmmc0ext-clk {
1089 rockchip,pins =
1090 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1091 };
1092
1093 sdmmc0ext_cmd: sdmmc0ext-cmd {
1094 rockchip,pins =
1095 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1096 };
1097
1098 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1099 rockchip,pins =
1100 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1101 };
1102
1103 sdmmc0ext_dectn: sdmmc0ext-dectn {
1104 rockchip,pins =
1105 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1106 };
1107
1108 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1109 rockchip,pins =
1110 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1111 };
1112
1113 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1114 rockchip,pins =
1115 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1116 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1117 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1118 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1119 };
1120
1121 sdmmc0ext_gpio: sdmmc0ext-gpio {
1122 rockchip,pins =
1123 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1124 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1125 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1126 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1127 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1128 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1129 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1130 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1131 };
1132 };
1133
1134 sdmmc1 {
1135 sdmmc1_clk: sdmmc1-clk {
1136 rockchip,pins =
1137 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1138 };
1139
1140 sdmmc1_cmd: sdmmc1-cmd {
1141 rockchip,pins =
1142 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1143 };
1144
1145 sdmmc1_pwren: sdmmc1-pwren {
1146 rockchip,pins =
1147 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1148 };
1149
1150 sdmmc1_wrprt: sdmmc1-wrprt {
1151 rockchip,pins =
1152 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1153 };
1154
1155 sdmmc1_dectn: sdmmc1-dectn {
1156 rockchip,pins =
1157 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1158 };
1159
1160 sdmmc1_bus1: sdmmc1-bus1 {
1161 rockchip,pins =
1162 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1163 };
1164
1165 sdmmc1_bus4: sdmmc1-bus4 {
1166 rockchip,pins =
1167 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1168 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1169 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1170 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1171 };
1172
1173 sdmmc1_gpio: sdmmc1-gpio {
1174 rockchip,pins =
1175 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1176 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1177 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1178 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1179 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1180 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1181 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1182 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1183 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1184 };
1185 };
1186
1187 emmc {
1188 emmc_clk: emmc-clk {
1189 rockchip,pins =
1190 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1191 };
1192
1193 emmc_cmd: emmc-cmd {
1194 rockchip,pins =
1195 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1196 };
1197
1198 emmc_pwren: emmc-pwren {
1199 rockchip,pins =
1200 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1201 };
1202
1203 emmc_rstnout: emmc-rstnout {
1204 rockchip,pins =
1205 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1206 };
1207
1208 emmc_bus1: emmc-bus1 {
1209 rockchip,pins =
1210 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1211 };
1212
1213 emmc_bus4: emmc-bus4 {
1214 rockchip,pins =
1215 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1216 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1217 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1218 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1219 };
1220
1221 emmc_bus8: emmc-bus8 {
1222 rockchip,pins =
1223 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1224 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1225 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1226 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1227 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1228 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1229 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1230 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1231 };
1232 };
1233
1234 pwm0 {
1235 pwm0_pin: pwm0-pin {
1236 rockchip,pins =
1237 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1238 };
1239 };
1240
1241 pwm1 {
1242 pwm1_pin: pwm1-pin {
1243 rockchip,pins =
1244 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1245 };
1246 };
1247
1248 pwm2 {
1249 pwm2_pin: pwm2-pin {
1250 rockchip,pins =
1251 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1252 };
1253 };
1254
1255 pwmir {
1256 pwmir_pin: pwmir-pin {
1257 rockchip,pins =
1258 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1259 };
1260 };
1261
1262 gmac-0 {
1263 rgmiim0_pins: rgmiim0-pins {
1264 rockchip,pins =
1265 /* mac_txclk */
1266 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1267 /* mac_rxclk */
1268 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1269 /* mac_mdio */
1270 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1271 /* mac_txen */
1272 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1273 /* mac_clk */
1274 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1275 /* mac_rxdv */
1276 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1277 /* mac_mdc */
1278 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1279 /* mac_rxd1 */
1280 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1281 /* mac_rxd0 */
1282 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1283 /* mac_txd1 */
1284 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1285 /* mac_txd0 */
1286 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1287 /* mac_rxd3 */
1288 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1289 /* mac_rxd2 */
1290 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1291 /* mac_txd3 */
1292 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1293 /* mac_txd2 */
1294 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1295 };
1296
1297 rmiim0_pins: rmiim0-pins {
1298 rockchip,pins =
1299 /* mac_mdio */
1300 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1301 /* mac_txen */
1302 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1303 /* mac_clk */
1304 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1305 /* mac_rxer */
1306 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1307 /* mac_rxdv */
1308 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1309 /* mac_mdc */
1310 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1311 /* mac_rxd1 */
1312 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1313 /* mac_rxd0 */
1314 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1315 /* mac_txd1 */
1316 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1317 /* mac_txd0 */
1318 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1319 };
1320 };
1321
1322 gmac-1 {
1323 rgmiim1_pins: rgmiim1-pins {
1324 rockchip,pins =
1325 /* mac_txclk */
1326 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1327 /* mac_rxclk */
1328 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1329 /* mac_mdio */
1330 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1331 /* mac_txen */
1332 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1333 /* mac_clk */
1334 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1335 /* mac_rxdv */
1336 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1337 /* mac_mdc */
1338 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1339 /* mac_rxd1 */
1340 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1341 /* mac_rxd0 */
1342 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1343 /* mac_txd1 */
1344 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1345 /* mac_txd0 */
1346 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1347 /* mac_rxd3 */
1348 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1349 /* mac_rxd2 */
1350 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1351 /* mac_txd3 */
1352 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1353 /* mac_txd2 */
1354 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1355
1356 /* mac_txclk */
1357 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1358 /* mac_txen */
1359 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1360 /* mac_clk */
1361 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1362 /* mac_txd1 */
1363 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1364 /* mac_txd0 */
1365 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1366 /* mac_txd3 */
1367 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1368 /* mac_txd2 */
1369 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1370 };
1371
1372 rmiim1_pins: rmiim1-pins {
1373 rockchip,pins =
1374 /* mac_mdio */
1375 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1376 /* mac_txen */
1377 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1378 /* mac_clk */
1379 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1380 /* mac_rxer */
1381 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1382 /* mac_rxdv */
1383 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1384 /* mac_mdc */
1385 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1386 /* mac_rxd1 */
1387 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1388 /* mac_rxd0 */
1389 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1390 /* mac_txd1 */
1391 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1392 /* mac_txd0 */
1393 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1394
1395 /* mac_mdio */
1396 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1397 /* mac_txen */
1398 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1399 /* mac_clk */
1400 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1401 /* mac_mdc */
1402 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1403 /* mac_txd1 */
1404 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1405 /* mac_txd0 */
1406 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1407 };
1408 };
1409
1410 gmac2phy {
1411 fephyled_speed100: fephyled-speed100 {
1412 rockchip,pins =
1413 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1414 };
1415
1416 fephyled_speed10: fephyled-speed10 {
1417 rockchip,pins =
1418 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1419 };
1420
1421 fephyled_duplex: fephyled-duplex {
1422 rockchip,pins =
1423 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1424 };
1425
1426 fephyled_rxm0: fephyled-rxm0 {
1427 rockchip,pins =
1428 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1429 };
1430
1431 fephyled_txm0: fephyled-txm0 {
1432 rockchip,pins =
1433 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1434 };
1435
1436 fephyled_linkm0: fephyled-linkm0 {
1437 rockchip,pins =
1438 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1439 };
1440
1441 fephyled_rxm1: fephyled-rxm1 {
1442 rockchip,pins =
1443 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1444 };
1445
1446 fephyled_txm1: fephyled-txm1 {
1447 rockchip,pins =
1448 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1449 };
1450
1451 fephyled_linkm1: fephyled-linkm1 {
1452 rockchip,pins =
1453 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1454 };
1455 };
1456
1457 tsadc_pin {
1458 tsadc_int: tsadc-int {
1459 rockchip,pins =
1460 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1461 };
1462 tsadc_gpio: tsadc-gpio {
1463 rockchip,pins =
1464 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1465 };
1466 };
1467
1468 hdmi_pin {
1469 hdmi_cec: hdmi-cec {
1470 rockchip,pins =
1471 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1472 };
1473
1474 hdmi_hpd: hdmi-hpd {
1475 rockchip,pins =
1476 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1477 };
1478 };
1479
1480 cif-0 {
1481 dvp_d2d9_m0:dvp-d2d9-m0 {
1482 rockchip,pins =
1483 /* cif_d0 */
1484 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1485 /* cif_d1 */
1486 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1487 /* cif_d2 */
1488 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1489 /* cif_d3 */
1490 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1491 /* cif_d4 */
1492 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1493 /* cif_d5m0 */
1494 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1495 /* cif_d6m0 */
1496 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1497 /* cif_d7m0 */
1498 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1499 /* cif_href */
1500 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1501 /* cif_vsync */
1502 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1503 /* cif_clkoutm0 */
1504 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1505 /* cif_clkin */
1506 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1507 };
1508 };
1509
1510 cif-1 {
1511 dvp_d2d9_m1:dvp-d2d9-m1 {
1512 rockchip,pins =
1513 /* cif_d0 */
1514 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1515 /* cif_d1 */
1516 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1517 /* cif_d2 */
1518 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1519 /* cif_d3 */
1520 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1521 /* cif_d4 */
1522 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1523 /* cif_d5m1 */
1524 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1525 /* cif_d6m1 */
1526 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1527 /* cif_d7m1 */
1528 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1529 /* cif_href */
1530 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1531 /* cif_vsync */
1532 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1533 /* cif_clkoutm1 */
1534 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1535 /* cif_clkin */
1536 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1537 };
1538 };
1539 };
1540};