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git01.mediatek.com / filogic / uboot / 820d1128716db29ec4cea4f9bdb025be4cd5661a / . / arch / arm / dts / rk3328.dtsi
blob: f18cfc26279c1571dd03eb76c042df76618a82a4 [file] [log] [blame]
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]1/*
2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <dt-bindings/clock/rk3328-cru.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12
13/ {
14 compatible = "rockchip,rk3328";
15
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 };
29
30 cpus {
31 #address-cells = <2>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53", "arm,armv8";
37 reg = <0x0 0x0>;
38 enable-method = "psci";
39// clocks = <&cru ARMCLK>;
40 operating-points-v2 = <&cpu0_opp_table>;
41 };
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53", "arm,armv8";
45 reg = <0x0 0x1>;
46 enable-method = "psci";
47 };
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a53", "arm,armv8";
51 reg = <0x0 0x2>;
52 enable-method = "psci";
53 };
54 cpu3: cpu@3 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a53", "arm,armv8";
57 reg = <0x0 0x3>;
58 enable-method = "psci";
59 };
60 };
61
62 cpu0_opp_table: opp_table0 {
63 compatible = "operating-points-v2";
64 opp-shared;
65
66 opp@408000000 {
67 opp-hz = /bits/ 64 <408000000>;
68 opp-microvolt = <950000>;
69 clock-latency-ns = <40000>;
70 opp-suspend;
71 };
72 opp@600000000 {
73 opp-hz = /bits/ 64 <600000000>;
74 opp-microvolt = <950000>;
75 clock-latency-ns = <40000>;
76 };
77 opp@816000000 {
78 opp-hz = /bits/ 64 <816000000>;
79 opp-microvolt = <1000000>;
80 clock-latency-ns = <40000>;
81 };
82 opp@1008000000 {
83 opp-hz = /bits/ 64 <1008000000>;
84 opp-microvolt = <1100000>;
85 clock-latency-ns = <40000>;
86 };
87 opp@1200000000 {
88 opp-hz = /bits/ 64 <1200000000>;
89 opp-microvolt = <1225000>;
90 clock-latency-ns = <40000>;
91 };
92 opp@1296000000 {
93 opp-hz = /bits/ 64 <1296000000>;
94 opp-microvolt = <1300000>;
95 clock-latency-ns = <40000>;
96 };
97 };
98
99 arm-pmu {
100 compatible = "arm,cortex-a53-pmu";
101 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
105 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
106 };
107
108 psci {
109 compatible = "arm,psci-1.0";
110 method = "smc";
111 };
112
113 timer {
114 compatible = "arm,armv8-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
119 };
120
121 xin24m: xin24m {
122 compatible = "fixed-clock";
123 #clock-cells = <0>;
124 clock-frequency = <24000000>;
125 clock-output-names = "xin24m";
126 };
127
128 i2s0: i2s@ff000000 {
129 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
130 reg = <0x0 0xff000000 0x0 0x1000>;
131 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
133 clock-names = "i2s_clk", "i2s_hclk";
134 dmas = <&dmac 11>, <&dmac 12>;
135 #dma-cells = <2>;
136 dma-names = "tx", "rx";
137 status = "disabled";
138 };
139
140 i2s1: i2s@ff010000 {
141 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
142 reg = <0x0 0xff010000 0x0 0x1000>;
143 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
145 clock-names = "i2s_clk", "i2s_hclk";
146 dmas = <&dmac 14>, <&dmac 15>;
147 #dma-cells = <2>;
148 dma-names = "tx", "rx";
149 status = "disabled";
150 };
151
152 i2s2: i2s@ff020000 {
153 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
154 reg = <0x0 0xff020000 0x0 0x1000>;
155 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
157 clock-names = "i2s_clk", "i2s_hclk";
158 dmas = <&dmac 0>, <&dmac 1>;
159 #dma-cells = <2>;
160 dma-names = "tx", "rx";
161 pinctrl-names = "default", "sleep";
162 pinctrl-0 = <&i2s2m0_mclk
163 &i2s2m0_sclk
164 &i2s2m0_lrcktx
165 &i2s2m0_lrckrx
166 &i2s2m0_sdo
167 &i2s2m0_sdi>;
168 pinctrl-1 = <&i2s2m0_sleep>;
169 status = "disabled";
170 };
171
172 spdif: spdif@ff030000 {
173 compatible = "rockchip,rk3328-spdif";
174 reg = <0x0 0xff030000 0x0 0x1000>;
175 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
177 clock-names = "mclk", "hclk";
178 dmas = <&dmac 10>;
179 #dma-cells = <1>;
180 dma-names = "tx";
181 pinctrl-names = "default";
182 pinctrl-0 = <&spdifm2_tx>;
183 status = "disabled";
184 };
185
186 grf: syscon@ff100000 {
187 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
188 reg = <0x0 0xff100000 0x0 0x1000>;
189 #address-cells = <1>;
190 #size-cells = <1>;
191
192 io_domains: io-domains {
193 compatible = "rockchip,rk3328-io-voltage-domain";
194 status = "disabled";
195 };
196 };
197
198 uart0: serial@ff110000 {
199 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
200 reg = <0x0 0xff110000 0x0 0x100>;
201 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
203 clock-names = "baudclk", "apb_pclk";
204 reg-shift = <2>;
205 reg-io-width = <4>;
206 dmas = <&dmac 2>, <&dmac 3>;
207 #dma-cells = <2>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
210 status = "disabled";
211 };
212
213 uart1: serial@ff120000 {
214 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
215 reg = <0x0 0xff120000 0x0 0x100>;
216 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
218 clock-names = "sclk_uart", "pclk_uart";
219 reg-shift = <2>;
220 reg-io-width = <4>;
221 dmas = <&dmac 4>, <&dmac 5>;
222 #dma-cells = <2>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
225 status = "disabled";
226 };
227
228 uart2: serial@ff130000 {
229 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
230 reg = <0x0 0xff130000 0x0 0x100>;
231 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
233 clock-names = "baudclk", "apb_pclk";
234 clock-frequency = <24000000>;
235 reg-shift = <2>;
236 reg-io-width = <4>;
237 dmas = <&dmac 6>, <&dmac 7>;
238 #dma-cells = <2>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart2m1_xfer>;
241 status = "disabled";
242 };
243
244 pmu: power-management@ff140000 {
245 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
246 reg = <0x0 0xff140000 0x0 0x1000>;
247 };
248
249 i2c0: i2c@ff150000 {
250 compatible = "rockchip,rk3328-i2c";
251 reg = <0x0 0xff150000 0x0 0x1000>;
252 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
256 clock-names = "i2c", "pclk";
257 pinctrl-names = "default";
258 pinctrl-0 = <&i2c0_xfer>;
259 status = "disabled";
260 };
261
262 i2c1: i2c@ff160000 {
263 compatible = "rockchip,rk3328-i2c";
264 reg = <0x0 0xff160000 0x0 0x1000>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
267 #size-cells = <0>;
268 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
269 clock-names = "i2c", "pclk";
270 pinctrl-names = "default";
271 pinctrl-0 = <&i2c1_xfer>;
272 status = "disabled";
273 };
274
275 i2c2: i2c@ff170000 {
276 compatible = "rockchip,rk3328-i2c";
277 reg = <0x0 0xff170000 0x0 0x1000>;
278 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>;
280 #size-cells = <0>;
281 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
282 clock-names = "i2c", "pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled";
286 };
287
288 i2c3: i2c@ff180000 {
289 compatible = "rockchip,rk3328-i2c";
290 reg = <0x0 0xff180000 0x0 0x1000>;
291 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
295 clock-names = "i2c", "pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled";
299 };
300
301 spi0: spi@ff190000 {
302 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
303 reg = <0x0 0xff190000 0x0 0x1000>;
304 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
308 clock-names = "spiclk", "apb_pclk";
309 dmas = <&dmac 8>, <&dmac 9>;
310 #dma-cells = <2>;
311 dma-names = "tx", "rx";
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
314 status = "disabled";
315 };
316
317 wdt: watchdog@ff1a0000 {
318 compatible = "snps,dw-wdt";
319 reg = <0x0 0xff1a0000 0x0 0x100>;
320 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
321 status = "disabled";
322 };
323
324 amba {
325 compatible = "simple-bus";
326 #address-cells = <2>;
327 #size-cells = <2>;
328 ranges;
329
330 dmac: dmac@ff1f0000 {
331 compatible = "arm,pl330", "arm,primecell";
332 reg = <0x0 0xff1f0000 0x0 0x4000>;
333 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&cru ACLK_DMAC>;
336 clock-names = "apb_pclk";
337 #dma-cells = <1>;
338 };
339 };
340
341 saradc: saradc@ff280000 {
342 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
343 reg = <0x0 0xff280000 0x0 0x100>;
344 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
345 #io-channel-cells = <1>;
346 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
347 clock-names = "saradc", "apb_pclk";
348 resets = <&cru SRST_SARADC_P>;
349 reset-names = "saradc-apb";
350 status = "disabled";
351 };
352
353 cru: clock-controller@ff440000 {
354 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
355 reg = <0x0 0xff440000 0x0 0x1000>;
356 rockchip,grf = <&grf>;
357 #clock-cells = <1>;
358 #reset-cells = <1>;
359 assigned-clocks =
360 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
361 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
362 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
363 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
364 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
365 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
366 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
367 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
368 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
369 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
370 <&cru SCLK_WIFI>, <&cru ARMCLK>,
371 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
372 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
373 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
374 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
375 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
376 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
377 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
378 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
379 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
380 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
381 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
382 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
383 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
384 assigned-clock-parents =
385 <&cru HDMIPHY>, <&cru PLL_APLL>,
386 <&cru PLL_GPLL>, <&xin24m>,
387 <&xin24m>, <&xin24m>;
388 assigned-clock-rates =
389 <0>, <61440000>,
390 <0>, <24000000>,
391 <24000000>, <24000000>,
392 <15000000>, <15000000>,
393 <100000000>, <100000000>,
394 <100000000>, <100000000>,
395 <50000000>, <100000000>,
396 <100000000>, <100000000>,
397 <50000000>, <50000000>,
398 <50000000>, <50000000>,
399 <24000000>, <600000000>,
400 <491520000>, <1200000000>,
401 <150000000>, <75000000>,
402 <75000000>, <150000000>,
403 <75000000>, <75000000>,
404 <300000000>, <100000000>,
405 <300000000>, <200000000>,
406 <400000000>, <500000000>,
407 <200000000>, <300000000>,
408 <300000000>, <250000000>,
409 <200000000>, <100000000>,
410 <24000000>, <100000000>,
411 <150000000>, <50000000>,
412 <32768>, <32768>;
413 };
414
415 sdmmc: rksdmmc@ff500000 {
416 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
417 reg = <0x0 0xff500000 0x0 0x4000>;
418 clock-freq-min-max = <400000 150000000>;
419 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
420 clock-names = "biu", "ciu";
421 fifo-depth = <0x100>;
422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
423 status = "disabled";
424 };
425
426 sdio: dwmmc@ff510000 {
427 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
428 reg = <0x0 0xff510000 0x0 0x4000>;
429 clock-freq-min-max = <400000 150000000>;
430 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
431 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
432 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
433 fifo-depth = <0x100>;
434 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
435 status = "disabled";
436 };
437
438 emmc: rksdmmc@ff520000 {
439 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
440 reg = <0x0 0xff520000 0x0 0x4000>;
441 clock-freq-min-max = <400000 150000000>;
442 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
443 clock-names = "biu", "ciu";
444 fifo-depth = <0x100>;
445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
446 status = "disabled";
447 };
448
Meng Dongyang4fd2d8f2017-05-17 18:21:46 +0800[diff] [blame]449 usb_host0_ehci: usb@ff5c0000 {
450 compatible = "generic-ehci";
451 reg = <0x0 0xff5c0000 0x0 0x10000>;
452 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
453 status = "disabled";
454 };
455
456 usb_host0_ohci: usb@ff5d0000 {
457 compatible = "generic-ohci";
458 reg = <0x0 0xff5d0000 0x0 0x10000>;
459 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
460 status = "disabled";
461 };
462
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]463 sdmmc_ext: rksdmmc@ff5f0000 {
464 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
465 reg = <0x0 0xff5f0000 0x0 0x4000>;
466 clock-freq-min-max = <400000 150000000>;
467 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
468 clock-names = "biu", "ciu";
469 fifo-depth = <0x100>;
470 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
471 status = "disabled";
472 };
473
Meng Dongyang820d1122017-05-17 18:25:28 +0800[diff] [blame^]474 usb_host0_xhci: usb@ff600000 {
475 compatible = "rockchip,rk3328-xhci";
476 reg = <0x0 0xff600000 0x0 0x100000>;
477 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
478 snps,dis-enblslpm-quirk;
479 snps,phyif-utmi-bits = <16>;
480 snps,dis-u2-freeclk-exists-quirk;
481 snps,dis-u2-susphy-quirk;
482 status = "disabled";
483 };
484
Kever Yangfc281b72017-02-23 15:37:50 +0800[diff] [blame]485 gic: interrupt-controller@ffb70000 {
486 compatible = "arm,gic-400";
487 #interrupt-cells = <3>;
488 #address-cells = <0>;
489 interrupt-controller;
490 reg = <0x0 0xff811000 0 0x1000>,
491 <0x0 0xff812000 0 0x2000>,
492 <0x0 0xff814000 0 0x2000>,
493 <0x0 0xff816000 0 0x2000>;
494 interrupts = <GIC_PPI 9
495 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
496 };
497
498 pinctrl: pinctrl {
499 compatible = "rockchip,rk3328-pinctrl";
500 rockchip,grf = <&grf>;
501 #address-cells = <2>;
502 #size-cells = <2>;
503 ranges;
504
505 gpio0: gpio0@ff210000 {
506 compatible = "rockchip,gpio-bank";
507 reg = <0x0 0xff210000 0x0 0x100>;
508 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&cru PCLK_GPIO0>;
510
511 gpio-controller;
512 #gpio-cells = <2>;
513
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 };
517
518 gpio1: gpio1@ff220000 {
519 compatible = "rockchip,gpio-bank";
520 reg = <0x0 0xff220000 0x0 0x100>;
521 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru PCLK_GPIO1>;
523
524 gpio-controller;
525 #gpio-cells = <2>;
526
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 };
530
531 gpio2: gpio2@ff230000 {
532 compatible = "rockchip,gpio-bank";
533 reg = <0x0 0xff230000 0x0 0x100>;
534 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&cru PCLK_GPIO2>;
536
537 gpio-controller;
538 #gpio-cells = <2>;
539
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 };
543
544 gpio3: gpio3@ff240000 {
545 compatible = "rockchip,gpio-bank";
546 reg = <0x0 0xff240000 0x0 0x100>;
547 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru PCLK_GPIO3>;
549
550 gpio-controller;
551 #gpio-cells = <2>;
552
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 };
556
557 pcfg_pull_up: pcfg-pull-up {
558 bias-pull-up;
559 };
560
561 pcfg_pull_down: pcfg-pull-down {
562 bias-pull-down;
563 };
564
565 pcfg_pull_none: pcfg-pull-none {
566 bias-disable;
567 };
568
569 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
570 bias-disable;
571 drive-strength = <2>;
572 };
573
574 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
575 bias-pull-up;
576 drive-strength = <2>;
577 };
578
579 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
580 bias-pull-up;
581 drive-strength = <4>;
582 };
583
584 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
585 bias-disable;
586 drive-strength = <4>;
587 };
588
589 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
590 bias-pull-down;
591 drive-strength = <4>;
592 };
593
594 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
595 bias-disable;
596 drive-strength = <8>;
597 };
598
599 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
600 bias-pull-up;
601 drive-strength = <8>;
602 };
603
604 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
605 bias-disable;
606 drive-strength = <12>;
607 };
608
609 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
610 bias-pull-up;
611 drive-strength = <12>;
612 };
613
614 pcfg_output_high: pcfg-output-high {
615 output-high;
616 };
617
618 pcfg_output_low: pcfg-output-low {
619 output-low;
620 };
621
622 pcfg_input_high: pcfg-input-high {
623 bias-pull-up;
624 input-enable;
625 };
626
627 pcfg_input: pcfg-input {
628 input-enable;
629 };
630
631 i2c0 {
632 i2c0_xfer: i2c0-xfer {
633 rockchip,pins =
634 <2 24 RK_FUNC_1 &pcfg_pull_none>,
635 <2 25 RK_FUNC_1 &pcfg_pull_none>;
636 };
637 };
638
639 i2c1 {
640 i2c1_xfer: i2c1-xfer {
641 rockchip,pins =
642 <2 4 RK_FUNC_2 &pcfg_pull_none>,
643 <2 5 RK_FUNC_2 &pcfg_pull_none>;
644 };
645 };
646
647 i2c2 {
648 i2c2_xfer: i2c2-xfer {
649 rockchip,pins =
650 <2 13 RK_FUNC_1 &pcfg_pull_none>,
651 <2 14 RK_FUNC_1 &pcfg_pull_none>;
652 };
653 };
654
655 i2c3 {
656 i2c3_xfer: i2c3-xfer {
657 rockchip,pins =
658 <0 5 RK_FUNC_2 &pcfg_pull_none>,
659 <0 6 RK_FUNC_2 &pcfg_pull_none>;
660 };
661 i2c3_gpio: i2c3-gpio {
662 rockchip,pins =
663 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
664 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
665 };
666 };
667
668 hdmi_i2c {
669 hdmii2c_xfer: hdmii2c-xfer {
670 rockchip,pins =
671 <0 5 RK_FUNC_1 &pcfg_pull_none>,
672 <0 6 RK_FUNC_1 &pcfg_pull_none>;
673 };
674 };
675
676 uart0 {
677 uart0_xfer: uart0-xfer {
678 rockchip,pins =
679 <1 9 RK_FUNC_1 &pcfg_pull_up>,
680 <1 8 RK_FUNC_1 &pcfg_pull_none>;
681 };
682
683 uart0_cts: uart0-cts {
684 rockchip,pins =
685 <1 11 RK_FUNC_1 &pcfg_pull_none>;
686 };
687
688 uart0_rts: uart0-rts {
689 rockchip,pins =
690 <1 10 RK_FUNC_1 &pcfg_pull_none>;
691 };
692
693 uart0_rts_gpio: uart0-rts-gpio {
694 rockchip,pins =
695 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
696 };
697 };
698
699 uart1 {
700 uart1_xfer: uart1-xfer {
701 rockchip,pins =
702 <3 4 RK_FUNC_4 &pcfg_pull_up>,
703 <3 6 RK_FUNC_4 &pcfg_pull_none>;
704 };
705
706 uart1_cts: uart1-cts {
707 rockchip,pins =
708 <3 7 RK_FUNC_4 &pcfg_pull_none>;
709 };
710
711 uart1_rts: uart1-rts {
712 rockchip,pins =
713 <3 5 RK_FUNC_4 &pcfg_pull_none>;
714 };
715
716 uart1_rts_gpio: uart1-rts-gpio {
717 rockchip,pins =
718 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
719 };
720 };
721
722 uart2-0 {
723 uart2m0_xfer: uart2m0-xfer {
724 rockchip,pins =
725 <1 0 RK_FUNC_2 &pcfg_pull_up>,
726 <1 1 RK_FUNC_2 &pcfg_pull_none>;
727 };
728 };
729
730 uart2-1 {
731 uart2m1_xfer: uart2m1-xfer {
732 rockchip,pins =
733 <2 0 RK_FUNC_1 &pcfg_pull_up>,
734 <2 1 RK_FUNC_1 &pcfg_pull_none>;
735 };
736 };
737
738 spi0-0 {
739 spi0m0_clk: spi0m0-clk {
740 rockchip,pins =
741 <2 8 RK_FUNC_1 &pcfg_pull_up>;
742 };
743
744 spi0m0_cs0: spi0m0-cs0 {
745 rockchip,pins =
746 <2 11 RK_FUNC_1 &pcfg_pull_up>;
747 };
748
749 spi0m0_tx: spi0m0-tx {
750 rockchip,pins =
751 <2 9 RK_FUNC_1 &pcfg_pull_up>;
752 };
753
754 spi0m0_rx: spi0m0-rx {
755 rockchip,pins =
756 <2 10 RK_FUNC_1 &pcfg_pull_up>;
757 };
758
759 spi0m0_cs1: spi0m0-cs1 {
760 rockchip,pins =
761 <2 12 RK_FUNC_1 &pcfg_pull_up>;
762 };
763 };
764
765 spi0-1 {
766 spi0m1_clk: spi0m1-clk {
767 rockchip,pins =
768 <3 23 RK_FUNC_2 &pcfg_pull_up>;
769 };
770
771 spi0m1_cs0: spi0m1-cs0 {
772 rockchip,pins =
773 <3 26 RK_FUNC_2 &pcfg_pull_up>;
774 };
775
776 spi0m1_tx: spi0m1-tx {
777 rockchip,pins =
778 <3 25 RK_FUNC_2 &pcfg_pull_up>;
779 };
780
781 spi0m1_rx: spi0m1-rx {
782 rockchip,pins =
783 <3 24 RK_FUNC_2 &pcfg_pull_up>;
784 };
785
786 spi0m1_cs1: spi0m1-cs1 {
787 rockchip,pins =
788 <3 27 RK_FUNC_2 &pcfg_pull_up>;
789 };
790 };
791
792 spi0-2 {
793 spi0m2_clk: spi0m2-clk {
794 rockchip,pins =
795 <3 0 RK_FUNC_4 &pcfg_pull_up>;
796 };
797
798 spi0m2_cs0: spi0m2-cs0 {
799 rockchip,pins =
800 <3 8 RK_FUNC_3 &pcfg_pull_up>;
801 };
802
803 spi0m2_tx: spi0m2-tx {
804 rockchip,pins =
805 <3 1 RK_FUNC_4 &pcfg_pull_up>;
806 };
807
808 spi0m2_rx: spi0m2-rx {
809 rockchip,pins =
810 <3 2 RK_FUNC_4 &pcfg_pull_up>;
811 };
812 };
813
814 i2s1 {
815 i2s1_mclk: i2s1-mclk {
816 rockchip,pins =
817 <2 15 RK_FUNC_1 &pcfg_pull_none>;
818 };
819
820 i2s1_sclk: i2s1-sclk {
821 rockchip,pins =
822 <2 18 RK_FUNC_1 &pcfg_pull_none>;
823 };
824
825 i2s1_lrckrx: i2s1-lrckrx {
826 rockchip,pins =
827 <2 16 RK_FUNC_1 &pcfg_pull_none>;
828 };
829
830 i2s1_lrcktx: i2s1-lrcktx {
831 rockchip,pins =
832 <2 17 RK_FUNC_1 &pcfg_pull_none>;
833 };
834
835 i2s1_sdi: i2s1-sdi {
836 rockchip,pins =
837 <2 19 RK_FUNC_1 &pcfg_pull_none>;
838 };
839
840 i2s1_sdo: i2s1-sdo {
841 rockchip,pins =
842 <2 23 RK_FUNC_1 &pcfg_pull_none>;
843 };
844
845 i2s1_sdio1: i2s1-sdio1 {
846 rockchip,pins =
847 <2 20 RK_FUNC_1 &pcfg_pull_none>;
848 };
849
850 i2s1_sdio2: i2s1-sdio2 {
851 rockchip,pins =
852 <2 21 RK_FUNC_1 &pcfg_pull_none>;
853 };
854
855 i2s1_sdio3: i2s1-sdio3 {
856 rockchip,pins =
857 <2 22 RK_FUNC_1 &pcfg_pull_none>;
858 };
859
860 i2s1_sleep: i2s1-sleep {
861 rockchip,pins =
862 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
863 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
864 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
865 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
866 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
867 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
868 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
869 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
870 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
871 };
872 };
873
874 i2s2-0 {
875 i2s2m0_mclk: i2s2m0-mclk {
876 rockchip,pins =
877 <1 21 RK_FUNC_1 &pcfg_pull_none>;
878 };
879
880 i2s2m0_sclk: i2s2m0-sclk {
881 rockchip,pins =
882 <1 22 RK_FUNC_1 &pcfg_pull_none>;
883 };
884
885 i2s2m0_lrckrx: i2s2m0-lrckrx {
886 rockchip,pins =
887 <1 26 RK_FUNC_1 &pcfg_pull_none>;
888 };
889
890 i2s2m0_lrcktx: i2s2m0-lrcktx {
891 rockchip,pins =
892 <1 23 RK_FUNC_1 &pcfg_pull_none>;
893 };
894
895 i2s2m0_sdi: i2s2m0-sdi {
896 rockchip,pins =
897 <1 24 RK_FUNC_1 &pcfg_pull_none>;
898 };
899
900 i2s2m0_sdo: i2s2m0-sdo {
901 rockchip,pins =
902 <1 25 RK_FUNC_1 &pcfg_pull_none>;
903 };
904
905 i2s2m0_sleep: i2s2m0-sleep {
906 rockchip,pins =
907 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
908 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
909 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
910 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
911 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
912 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
913 };
914 };
915
916 i2s2-1 {
917 i2s2m1_mclk: i2s2m1-mclk {
918 rockchip,pins =
919 <1 21 RK_FUNC_1 &pcfg_pull_none>;
920 };
921
922 i2s2m1_sclk: i2s2m1-sclk {
923 rockchip,pins =
924 <3 0 RK_FUNC_6 &pcfg_pull_none>;
925 };
926
927 i2s2m1_lrckrx: i2sm1-lrckrx {
928 rockchip,pins =
929 <3 8 RK_FUNC_6 &pcfg_pull_none>;
930 };
931
932 i2s2m1_lrcktx: i2s2m1-lrcktx {
933 rockchip,pins =
934 <3 8 RK_FUNC_4 &pcfg_pull_none>;
935 };
936
937 i2s2m1_sdi: i2s2m1-sdi {
938 rockchip,pins =
939 <3 2 RK_FUNC_6 &pcfg_pull_none>;
940 };
941
942 i2s2m1_sdo: i2s2m1-sdo {
943 rockchip,pins =
944 <3 1 RK_FUNC_6 &pcfg_pull_none>;
945 };
946
947 i2s2m1_sleep: i2s2m1-sleep {
948 rockchip,pins =
949 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
950 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
951 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
952 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
953 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
954 };
955 };
956
957 spdif-0 {
958 spdifm0_tx: spdifm0-tx {
959 rockchip,pins =
960 <0 27 RK_FUNC_1 &pcfg_pull_none>;
961 };
962 };
963
964 spdif-1 {
965 spdifm1_tx: spdifm1-tx {
966 rockchip,pins =
967 <2 17 RK_FUNC_2 &pcfg_pull_none>;
968 };
969 };
970
971 spdif-2 {
972 spdifm2_tx: spdifm2-tx {
973 rockchip,pins =
974 <0 2 RK_FUNC_2 &pcfg_pull_none>;
975 };
976 };
977
978 sdmmc0-0 {
979 sdmmc0m0_pwren: sdmmc0m0-pwren {
980 rockchip,pins =
981 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
982 };
983
984 sdmmc0m0_gpio: sdmmc0m0-gpio {
985 rockchip,pins =
986 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
987 };
988 };
989
990 sdmmc0-1 {
991 sdmmc0m1_pwren: sdmmc0m1-pwren {
992 rockchip,pins =
993 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
994 };
995
996 sdmmc0m1_gpio: sdmmc0m1-gpio {
997 rockchip,pins =
998 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
999 };
1000 };
1001
1002 sdmmc0 {
1003 sdmmc0_clk: sdmmc0-clk {
1004 rockchip,pins =
1005 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1006 };
1007
1008 sdmmc0_cmd: sdmmc0-cmd {
1009 rockchip,pins =
1010 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1011 };
1012
1013 sdmmc0_dectn: sdmmc0-dectn {
1014 rockchip,pins =
1015 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1016 };
1017
1018 sdmmc0_wrprt: sdmmc0-wrprt {
1019 rockchip,pins =
1020 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1021 };
1022
1023 sdmmc0_bus1: sdmmc0-bus1 {
1024 rockchip,pins =
1025 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1026 };
1027
1028 sdmmc0_bus4: sdmmc0-bus4 {
1029 rockchip,pins =
1030 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1031 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1032 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1033 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1034 };
1035
1036 sdmmc0_gpio: sdmmc0-gpio {
1037 rockchip,pins =
1038 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1039 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1040 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1041 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1042 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1043 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1044 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1045 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1046 };
1047 };
1048
1049 sdmmc0ext {
1050 sdmmc0ext_clk: sdmmc0ext-clk {
1051 rockchip,pins =
1052 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1053 };
1054
1055 sdmmc0ext_cmd: sdmmc0ext-cmd {
1056 rockchip,pins =
1057 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1058 };
1059
1060 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1061 rockchip,pins =
1062 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1063 };
1064
1065 sdmmc0ext_dectn: sdmmc0ext-dectn {
1066 rockchip,pins =
1067 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1068 };
1069
1070 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1071 rockchip,pins =
1072 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1073 };
1074
1075 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1076 rockchip,pins =
1077 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1078 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1079 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1080 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1081 };
1082
1083 sdmmc0ext_gpio: sdmmc0ext-gpio {
1084 rockchip,pins =
1085 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1086 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1087 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1088 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1089 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1090 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1091 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1092 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1093 };
1094 };
1095
1096 sdmmc1 {
1097 sdmmc1_clk: sdmmc1-clk {
1098 rockchip,pins =
1099 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1100 };
1101
1102 sdmmc1_cmd: sdmmc1-cmd {
1103 rockchip,pins =
1104 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1105 };
1106
1107 sdmmc1_pwren: sdmmc1-pwren {
1108 rockchip,pins =
1109 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1110 };
1111
1112 sdmmc1_wrprt: sdmmc1-wrprt {
1113 rockchip,pins =
1114 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1115 };
1116
1117 sdmmc1_dectn: sdmmc1-dectn {
1118 rockchip,pins =
1119 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1120 };
1121
1122 sdmmc1_bus1: sdmmc1-bus1 {
1123 rockchip,pins =
1124 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1125 };
1126
1127 sdmmc1_bus4: sdmmc1-bus4 {
1128 rockchip,pins =
1129 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1130 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1131 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1132 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1133 };
1134
1135 sdmmc1_gpio: sdmmc1-gpio {
1136 rockchip,pins =
1137 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1138 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1139 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1140 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1141 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1142 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1143 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1144 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1145 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1146 };
1147 };
1148
1149 emmc {
1150 emmc_clk: emmc-clk {
1151 rockchip,pins =
1152 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1153 };
1154
1155 emmc_cmd: emmc-cmd {
1156 rockchip,pins =
1157 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1158 };
1159
1160 emmc_pwren: emmc-pwren {
1161 rockchip,pins =
1162 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1163 };
1164
1165 emmc_rstnout: emmc-rstnout {
1166 rockchip,pins =
1167 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1168 };
1169
1170 emmc_bus1: emmc-bus1 {
1171 rockchip,pins =
1172 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1173 };
1174
1175 emmc_bus4: emmc-bus4 {
1176 rockchip,pins =
1177 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1178 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1179 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1180 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1181 };
1182
1183 emmc_bus8: emmc-bus8 {
1184 rockchip,pins =
1185 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1186 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1187 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1188 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1189 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1190 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1191 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1192 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1193 };
1194 };
1195
1196 pwm0 {
1197 pwm0_pin: pwm0-pin {
1198 rockchip,pins =
1199 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1200 };
1201 };
1202
1203 pwm1 {
1204 pwm1_pin: pwm1-pin {
1205 rockchip,pins =
1206 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1207 };
1208 };
1209
1210 pwm2 {
1211 pwm2_pin: pwm2-pin {
1212 rockchip,pins =
1213 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1214 };
1215 };
1216
1217 pwmir {
1218 pwmir_pin: pwmir-pin {
1219 rockchip,pins =
1220 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1221 };
1222 };
1223
1224 gmac-0 {
1225 rgmiim0_pins: rgmiim0-pins {
1226 rockchip,pins =
1227 /* mac_txclk */
1228 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1229 /* mac_rxclk */
1230 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1231 /* mac_mdio */
1232 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1233 /* mac_txen */
1234 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1235 /* mac_clk */
1236 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1237 /* mac_rxdv */
1238 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1239 /* mac_mdc */
1240 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1241 /* mac_rxd1 */
1242 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1243 /* mac_rxd0 */
1244 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1245 /* mac_txd1 */
1246 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1247 /* mac_txd0 */
1248 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1249 /* mac_rxd3 */
1250 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1251 /* mac_rxd2 */
1252 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1253 /* mac_txd3 */
1254 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1255 /* mac_txd2 */
1256 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1257 };
1258
1259 rmiim0_pins: rmiim0-pins {
1260 rockchip,pins =
1261 /* mac_mdio */
1262 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1263 /* mac_txen */
1264 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1265 /* mac_clk */
1266 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1267 /* mac_rxer */
1268 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1269 /* mac_rxdv */
1270 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1271 /* mac_mdc */
1272 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1273 /* mac_rxd1 */
1274 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1275 /* mac_rxd0 */
1276 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1277 /* mac_txd1 */
1278 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1279 /* mac_txd0 */
1280 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1281 };
1282 };
1283
1284 gmac-1 {
1285 rgmiim1_pins: rgmiim1-pins {
1286 rockchip,pins =
1287 /* mac_txclk */
1288 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1289 /* mac_rxclk */
1290 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1291 /* mac_mdio */
1292 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1293 /* mac_txen */
1294 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1295 /* mac_clk */
1296 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1297 /* mac_rxdv */
1298 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1299 /* mac_mdc */
1300 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1301 /* mac_rxd1 */
1302 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1303 /* mac_rxd0 */
1304 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1305 /* mac_txd1 */
1306 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1307 /* mac_txd0 */
1308 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1309 /* mac_rxd3 */
1310 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1311 /* mac_rxd2 */
1312 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1313 /* mac_txd3 */
1314 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1315 /* mac_txd2 */
1316 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1317
1318 /* mac_txclk */
1319 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1320 /* mac_txen */
1321 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1322 /* mac_clk */
1323 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1324 /* mac_txd1 */
1325 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1326 /* mac_txd0 */
1327 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1328 /* mac_txd3 */
1329 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1330 /* mac_txd2 */
1331 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1332 };
1333
1334 rmiim1_pins: rmiim1-pins {
1335 rockchip,pins =
1336 /* mac_mdio */
1337 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1338 /* mac_txen */
1339 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1340 /* mac_clk */
1341 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1342 /* mac_rxer */
1343 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1344 /* mac_rxdv */
1345 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1346 /* mac_mdc */
1347 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1348 /* mac_rxd1 */
1349 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1350 /* mac_rxd0 */
1351 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1352 /* mac_txd1 */
1353 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1354 /* mac_txd0 */
1355 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1356
1357 /* mac_mdio */
1358 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1359 /* mac_txen */
1360 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1361 /* mac_clk */
1362 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1363 /* mac_mdc */
1364 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1365 /* mac_txd1 */
1366 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1367 /* mac_txd0 */
1368 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1369 };
1370 };
1371
1372 gmac2phy {
1373 fephyled_speed100: fephyled-speed100 {
1374 rockchip,pins =
1375 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1376 };
1377
1378 fephyled_speed10: fephyled-speed10 {
1379 rockchip,pins =
1380 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1381 };
1382
1383 fephyled_duplex: fephyled-duplex {
1384 rockchip,pins =
1385 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1386 };
1387
1388 fephyled_rxm0: fephyled-rxm0 {
1389 rockchip,pins =
1390 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1391 };
1392
1393 fephyled_txm0: fephyled-txm0 {
1394 rockchip,pins =
1395 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1396 };
1397
1398 fephyled_linkm0: fephyled-linkm0 {
1399 rockchip,pins =
1400 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1401 };
1402
1403 fephyled_rxm1: fephyled-rxm1 {
1404 rockchip,pins =
1405 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1406 };
1407
1408 fephyled_txm1: fephyled-txm1 {
1409 rockchip,pins =
1410 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1411 };
1412
1413 fephyled_linkm1: fephyled-linkm1 {
1414 rockchip,pins =
1415 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1416 };
1417 };
1418
1419 tsadc_pin {
1420 tsadc_int: tsadc-int {
1421 rockchip,pins =
1422 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1423 };
1424 tsadc_gpio: tsadc-gpio {
1425 rockchip,pins =
1426 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1427 };
1428 };
1429
1430 hdmi_pin {
1431 hdmi_cec: hdmi-cec {
1432 rockchip,pins =
1433 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1434 };
1435
1436 hdmi_hpd: hdmi-hpd {
1437 rockchip,pins =
1438 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1439 };
1440 };
1441
1442 cif-0 {
1443 dvp_d2d9_m0:dvp-d2d9-m0 {
1444 rockchip,pins =
1445 /* cif_d0 */
1446 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1447 /* cif_d1 */
1448 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1449 /* cif_d2 */
1450 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1451 /* cif_d3 */
1452 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1453 /* cif_d4 */
1454 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1455 /* cif_d5m0 */
1456 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1457 /* cif_d6m0 */
1458 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1459 /* cif_d7m0 */
1460 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1461 /* cif_href */
1462 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1463 /* cif_vsync */
1464 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1465 /* cif_clkoutm0 */
1466 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1467 /* cif_clkin */
1468 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1469 };
1470 };
1471
1472 cif-1 {
1473 dvp_d2d9_m1:dvp-d2d9-m1 {
1474 rockchip,pins =
1475 /* cif_d0 */
1476 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1477 /* cif_d1 */
1478 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1479 /* cif_d2 */
1480 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1481 /* cif_d3 */
1482 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1483 /* cif_d4 */
1484 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1485 /* cif_d5m1 */
1486 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1487 /* cif_d6m1 */
1488 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1489 /* cif_d7m1 */
1490 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1491 /* cif_href */
1492 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1493 /* cif_vsync */
1494 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1495 /* cif_clkoutm1 */
1496 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1497 /* cif_clkin */
1498 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1499 };
1500 };
1501 };
1502};