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Gregory CLEMENTaf05ee52018-12-14 16:16:47 +01001/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2/*
3 * Copyright (c) 2018 Microsemi Corporation
4 */
5
6#ifndef __ASM_MACH_COMMON_H
7#define __ASM_MACH_COMMON_H
8
9#if defined(CONFIG_SOC_OCELOT)
10#include <mach/ocelot/ocelot.h>
11#include <mach/ocelot/ocelot_devcpu_gcb.h>
Lars Povlsen0ee16642018-12-20 09:56:02 +010012#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010013#include <mach/ocelot/ocelot_icpu_cfg.h>
Gregory CLEMENT819b57212018-12-14 16:16:48 +010014#elif defined(CONFIG_SOC_LUTON)
15#include <mach/luton/luton.h>
16#include <mach/luton/luton_devcpu_gcb.h>
Lars Povlsen0ee16642018-12-20 09:56:02 +010017#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
Gregory CLEMENT819b57212018-12-14 16:16:48 +010018#include <mach/luton/luton_icpu_cfg.h>
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010019#else
20#error Unsupported platform
21#endif
22
23#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
24#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
25#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
26#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
27
28#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
29
Lars Povlsen0ee16642018-12-20 09:56:02 +010030/* Common utility functions */
31
Lars Povlsenf01b7322019-01-08 10:38:33 +010032/*
33 * Perform a number of NOP instructions, blocks of 8 instructions.
34 * The (inlined) function will not affect cache or processor state.
35 */
36static inline void mscc_vcoreiii_nop_delay(int delay)
37{
38 while (delay > 0) {
39#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
40 switch (delay) {
41 case 8:
42 DELAY_8_NOPS();
43 /* fallthrough */
44 case 7:
45 DELAY_8_NOPS();
46 /* fallthrough */
47 case 6:
48 DELAY_8_NOPS();
49 /* fallthrough */
50 case 5:
51 DELAY_8_NOPS();
52 /* fallthrough */
53 case 4:
54 DELAY_8_NOPS();
55 /* fallthrough */
56 case 3:
57 DELAY_8_NOPS();
58 /* fallthrough */
59 case 2:
60 DELAY_8_NOPS();
61 /* fallthrough */
62 case 1:
63 DELAY_8_NOPS();
64 }
65 delay -= 8;
66#undef DELAY_8_NOPS
67 }
68}
69
Lars Povlsen0ee16642018-12-20 09:56:02 +010070int mscc_phy_rd_wr(u8 read,
71 u32 miim_controller,
72 u8 miim_addr,
73 u8 addr,
74 u16 *value);
75
76int mscc_phy_rd(u32 miim_controller,
77 u8 miim_addr,
78 u8 addr,
79 u16 *value);
80
81int mscc_phy_wr(u32 miim_controller,
82 u8 miim_addr,
83 u8 addr,
84 u16 value);
85
Lars Povlsen585078f2018-12-20 09:56:03 +010086void mscc_gpio_set_alternate(int gpio, int mode);
87
Gregory CLEMENTaf05ee52018-12-14 16:16:47 +010088#endif /* __ASM_MACH_COMMON_H */