| Chia-Wei Wang | 1c7ed53 | 2024-09-10 17:39:16 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (c) Aspeed Technology Inc. |
| 4 | */ |
| 5 | #ifndef __ASM_AST2700_SLI_H__ |
| 6 | #define __ASM_AST2700_SLI_H__ |
| 7 | |
| 8 | #define SLI_CPU_ADRBASE 0x12c17000 |
| 9 | #define SLI_IOD_ADRBASE 0x14c1e000 |
| 10 | #define SLIM_CPU_BASE (SLI_CPU_ADRBASE + 0x000) |
| 11 | #define SLIH_CPU_BASE (SLI_CPU_ADRBASE + 0x200) |
| 12 | #define SLIV_CPU_BASE (SLI_CPU_ADRBASE + 0x400) |
| 13 | #define SLIM_IOD_BASE (SLI_IOD_ADRBASE + 0x000) |
| 14 | #define SLIH_IOD_BASE (SLI_IOD_ADRBASE + 0x200) |
| 15 | #define SLIV_IOD_BASE (SLI_IOD_ADRBASE + 0x400) |
| 16 | |
| 17 | #define SLI_CTRL_I 0x00 |
| 18 | #define SLIV_RAW_MODE BIT(15) |
| 19 | #define SLI_TX_MODE BIT(14) |
| 20 | #define SLI_RX_PHY_LAH_SEL_REV BIT(13) |
| 21 | #define SLI_RX_PHY_LAH_SEL_NEG BIT(12) |
| 22 | #define SLI_AUTO_SEND_TRN_OFF BIT(8) |
| 23 | #define SLI_CLEAR_BUS BIT(6) |
| 24 | #define SLI_TRANS_EN BIT(5) |
| 25 | #define SLI_CLEAR_RX BIT(2) |
| 26 | #define SLI_CLEAR_TX BIT(1) |
| 27 | #define SLI_RESET_TRIGGER BIT(0) |
| 28 | #define SLI_CTRL_II 0x04 |
| 29 | #define SLI_CTRL_III 0x08 |
| 30 | #define SLI_CLK_SEL GENMASK(31, 28) |
| 31 | #define SLI_CLK_500M 0x6 |
| 32 | #define SLI_CLK_200M 0x3 |
| 33 | #define SLI_PHYCLK_SEL GENMASK(27, 24) |
| 34 | #define SLI_PHYCLK_25M 0x0 |
| 35 | #define SLI_PHYCLK_800M 0x1 |
| 36 | #define SLI_PHYCLK_400M 0x2 |
| 37 | #define SLI_PHYCLK_200M 0x3 |
| 38 | #define SLI_PHYCLK_788M 0x5 |
| 39 | #define SLI_PHYCLK_500M 0x6 |
| 40 | #define SLI_PHYCLK_250M 0x7 |
| 41 | #define SLIH_PAD_DLY_TX1 GENMASK(23, 18) |
| 42 | #define SLIH_PAD_DLY_TX0 GENMASK(17, 12) |
| 43 | #define SLIH_PAD_DLY_RX1 GENMASK(11, 6) |
| 44 | #define SLIH_PAD_DLY_RX0 GENMASK(5, 0) |
| 45 | #define SLIM_PAD_DLY_RX3 GENMASK(23, 18) |
| 46 | #define SLIM_PAD_DLY_RX2 GENMASK(17, 12) |
| 47 | #define SLIM_PAD_DLY_RX1 GENMASK(11, 6) |
| 48 | #define SLIM_PAD_DLY_RX0 GENMASK(5, 0) |
| 49 | #define SLI_CTRL_IV 0x0c |
| 50 | #define SLIM_PAD_DLY_TX3 GENMASK(23, 18) |
| 51 | #define SLIM_PAD_DLY_TX2 GENMASK(17, 12) |
| 52 | #define SLIM_PAD_DLY_TX1 GENMASK(11, 6) |
| 53 | #define SLIM_PAD_DLY_TX0 GENMASK(5, 0) |
| 54 | #define SLI_INTR_EN 0x10 |
| 55 | #define SLI_INTR_STATUS 0x14 |
| 56 | #define SLI_INTR_RX_SYNC BIT(15) |
| 57 | #define SLI_INTR_RX_ERR BIT(13) |
| 58 | #define SLI_INTR_RX_NACK BIT(12) |
| 59 | #define SLI_INTR_RX_TRAIN_PKT BIT(10) |
| 60 | #define SLI_INTR_RX_DISCONN BIT(6) |
| 61 | #define SLI_INTR_TX_SUSPEND BIT(4) |
| 62 | #define SLI_INTR_TX_TRAIN BIT(3) |
| 63 | #define SLI_INTR_TX_IDLE BIT(2) |
| 64 | #define SLI_INTR_RX_SUSPEND BIT(1) |
| 65 | #define SLI_INTR_RX_IDLE BIT(0) |
| 66 | #define SLI_INTR_RX_ERRORS \ |
| 67 | (SLI_INTR_RX_ERR | SLI_INTR_RX_NACK | SLI_INTR_RX_DISCONN) |
| 68 | |
| 69 | #define SLIM_MARB_FUNC_I 0x60 |
| 70 | #define SLIM_SLI_MARB_RR BIT(0) |
| 71 | |
| 72 | #define SLI_TARGET_PHYCLK SLI_PHYCLK_400M |
| 73 | #define SLIH_DEFAULT_DELAY 11 |
| 74 | #if (SLI_TARGET_PHYCLK == SLI_PHYCLK_800M) || (SLI_TARGET_PHYCLK == SLI_PHYCLK_788M) |
| 75 | #define SLIM_DEFAULT_DELAY 5 |
| 76 | #define SLIM_LAH_CONFIG 1 |
| 77 | #else |
| 78 | #define SLIM_DEFAULT_DELAY 12 |
| 79 | #define SLIM_LAH_CONFIG 0 |
| 80 | #endif |
| 81 | #endif |
| 82 | int sli_init(void); |