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Lei Wen142c8f92011-06-28 21:50:06 +00001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Lei Wen142c8f92011-06-28 21:50:06 +00006 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10
11#include <common.h>
Simon Glassb0842072016-06-12 23:30:27 -060012#include <errno.h>
Lei Wen142c8f92011-06-28 21:50:06 +000013#include <malloc.h>
14#include <mmc.h>
15#include <sdhci.h>
16
Stefan Roese13a547f2015-06-29 14:58:09 +020017#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
19#else
Lei Wen142c8f92011-06-28 21:50:06 +000020void *aligned_buffer;
Stefan Roese13a547f2015-06-29 14:58:09 +020021#endif
Lei Wen142c8f92011-06-28 21:50:06 +000022
23static void sdhci_reset(struct sdhci_host *host, u8 mask)
24{
25 unsigned long timeout;
26
27 /* Wait max 100 ms */
28 timeout = 100;
29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
31 if (timeout == 0) {
Darwin Rambo43558132013-12-19 15:13:25 -080032 printf("%s: Reset 0x%x never completed.\n",
33 __func__, (int)mask);
Lei Wen142c8f92011-06-28 21:50:06 +000034 return;
35 }
36 timeout--;
37 udelay(1000);
38 }
39}
40
41static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
42{
43 int i;
44 if (cmd->resp_type & MMC_RSP_136) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i = 0; i < 4; i++) {
47 cmd->response[i] = sdhci_readl(host,
48 SDHCI_RESPONSE + (3-i)*4) << 8;
49 if (i != 3)
50 cmd->response[i] |= sdhci_readb(host,
51 SDHCI_RESPONSE + (3-i)*4-1);
52 }
53 } else {
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
55 }
56}
57
58static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
59{
60 int i;
61 char *offs;
62 for (i = 0; i < data->blocksize; i += 4) {
63 offs = data->dest + i;
64 if (data->flags == MMC_DATA_READ)
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
66 else
67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
68 }
69}
70
71static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
72 unsigned int start_addr)
73{
Lei Wen6c13c662011-10-08 04:14:57 +000074 unsigned int stat, rdy, mask, timeout, block = 0;
Masahiro Yamada124f6ce2016-12-07 22:10:29 +090075#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chungf77f0582012-09-20 20:31:55 +000076 unsigned char ctrl;
Juhyun \(Justin\) Oh7d48a732013-09-13 18:06:00 +000077 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Jaehoon Chungf77f0582012-09-20 20:31:55 +000078 ctrl &= ~SDHCI_CTRL_DMA_MASK;
Juhyun \(Justin\) Oh7d48a732013-09-13 18:06:00 +000079 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chungf77f0582012-09-20 20:31:55 +000080#endif
Lei Wen142c8f92011-06-28 21:50:06 +000081
Jaehoon Chung30686bd2012-09-20 20:31:54 +000082 timeout = 1000000;
Lei Wen142c8f92011-06-28 21:50:06 +000083 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
84 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
85 do {
86 stat = sdhci_readl(host, SDHCI_INT_STATUS);
87 if (stat & SDHCI_INT_ERROR) {
Darwin Rambo43558132013-12-19 15:13:25 -080088 printf("%s: Error detected in status(0x%X)!\n",
89 __func__, stat);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +090090 return -EIO;
Lei Wen142c8f92011-06-28 21:50:06 +000091 }
92 if (stat & rdy) {
93 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
94 continue;
95 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
96 sdhci_transfer_pio(host, data);
97 data->dest += data->blocksize;
98 if (++block >= data->blocks)
99 break;
100 }
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900101#ifdef CONFIG_MMC_SDHCI_SDMA
Lei Wen142c8f92011-06-28 21:50:06 +0000102 if (stat & SDHCI_INT_DMA_END) {
103 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Lei Wen8241d402011-10-08 04:14:58 +0000104 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
Lei Wen142c8f92011-06-28 21:50:06 +0000105 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
106 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
107 }
108#endif
Lei Wen6c13c662011-10-08 04:14:57 +0000109 if (timeout-- > 0)
110 udelay(10);
111 else {
Darwin Rambo43558132013-12-19 15:13:25 -0800112 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900113 return -ETIMEDOUT;
Lei Wen6c13c662011-10-08 04:14:57 +0000114 }
Lei Wen142c8f92011-06-28 21:50:06 +0000115 } while (!(stat & SDHCI_INT_DATA_END));
116 return 0;
117}
118
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200119/*
120 * No command will be sent by driver if card is busy, so driver must wait
121 * for card ready state.
122 * Every time when card is busy after timeout then (last) timeout value will be
123 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada96250112016-08-25 16:07:39 +0900124 * Each function call will use last timeout value.
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200125 */
Masahiro Yamada96250112016-08-25 16:07:39 +0900126#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad4512312016-08-25 16:07:38 +0900127#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed4780832016-06-29 13:42:01 -0700128#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200129
Simon Glassb97f0fa2016-06-12 23:30:28 -0600130#ifdef CONFIG_DM_MMC_OPS
131static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
132 struct mmc_data *data)
133{
134 struct mmc *mmc = mmc_get_mmc_dev(dev);
135
136#else
Jeroen Hofsteeee54c7b2014-10-08 22:57:43 +0200137static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
Simon Glassb97f0fa2016-06-12 23:30:28 -0600138 struct mmc_data *data)
Lei Wen142c8f92011-06-28 21:50:06 +0000139{
Simon Glassb97f0fa2016-06-12 23:30:28 -0600140#endif
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200141 struct sdhci_host *host = mmc->priv;
Lei Wen142c8f92011-06-28 21:50:06 +0000142 unsigned int stat = 0;
143 int ret = 0;
144 int trans_bytes = 0, is_aligned = 1;
145 u32 mask, flags, mode;
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200146 unsigned int time = 0, start_addr = 0;
Simon Glass97c78e82016-05-14 14:03:04 -0600147 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Stefan Roese42817a42015-06-29 14:58:08 +0200148 unsigned start = get_timer(0);
Lei Wen142c8f92011-06-28 21:50:06 +0000149
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200150 /* Timeout unit - ms */
Masahiro Yamadad4512312016-08-25 16:07:38 +0900151 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wen142c8f92011-06-28 21:50:06 +0000152
153 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
154 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
155
156 /* We shouldn't wait for data inihibit for stop commands, even
157 though they might use busy signaling */
158 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
159 mask &= ~SDHCI_DATA_INHIBIT;
160
161 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200162 if (time >= cmd_timeout) {
Darwin Rambo43558132013-12-19 15:13:25 -0800163 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada96250112016-08-25 16:07:39 +0900164 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200165 cmd_timeout += cmd_timeout;
166 printf("timeout increasing to: %u ms.\n",
167 cmd_timeout);
168 } else {
169 puts("timeout.\n");
Jaehoon Chung7825d202016-07-19 16:33:36 +0900170 return -ECOMM;
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200171 }
Lei Wen142c8f92011-06-28 21:50:06 +0000172 }
Przemyslaw Marczakadccccf2013-10-08 18:12:09 +0200173 time++;
Lei Wen142c8f92011-06-28 21:50:06 +0000174 udelay(1000);
175 }
176
177 mask = SDHCI_INT_RESPONSE;
178 if (!(cmd->resp_type & MMC_RSP_PRESENT))
179 flags = SDHCI_CMD_RESP_NONE;
180 else if (cmd->resp_type & MMC_RSP_136)
181 flags = SDHCI_CMD_RESP_LONG;
182 else if (cmd->resp_type & MMC_RSP_BUSY) {
183 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chungd0d1b252016-07-12 21:18:46 +0900184 if (data)
185 mask |= SDHCI_INT_DATA_END;
Lei Wen142c8f92011-06-28 21:50:06 +0000186 } else
187 flags = SDHCI_CMD_RESP_SHORT;
188
189 if (cmd->resp_type & MMC_RSP_CRC)
190 flags |= SDHCI_CMD_CRC;
191 if (cmd->resp_type & MMC_RSP_OPCODE)
192 flags |= SDHCI_CMD_INDEX;
193 if (data)
194 flags |= SDHCI_CMD_DATA;
195
Darwin Rambo43558132013-12-19 15:13:25 -0800196 /* Set Transfer mode regarding to data flag */
Lei Wen142c8f92011-06-28 21:50:06 +0000197 if (data != 0) {
198 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
199 mode = SDHCI_TRNS_BLK_CNT_EN;
200 trans_bytes = data->blocks * data->blocksize;
201 if (data->blocks > 1)
202 mode |= SDHCI_TRNS_MULTI;
203
204 if (data->flags == MMC_DATA_READ)
205 mode |= SDHCI_TRNS_READ;
206
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900207#ifdef CONFIG_MMC_SDHCI_SDMA
Lei Wen142c8f92011-06-28 21:50:06 +0000208 if (data->flags == MMC_DATA_READ)
Rob Herring45ad2292015-03-17 15:46:38 -0500209 start_addr = (unsigned long)data->dest;
Lei Wen142c8f92011-06-28 21:50:06 +0000210 else
Rob Herring45ad2292015-03-17 15:46:38 -0500211 start_addr = (unsigned long)data->src;
Lei Wen142c8f92011-06-28 21:50:06 +0000212 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
213 (start_addr & 0x7) != 0x0) {
214 is_aligned = 0;
Rob Herring45ad2292015-03-17 15:46:38 -0500215 start_addr = (unsigned long)aligned_buffer;
Lei Wen142c8f92011-06-28 21:50:06 +0000216 if (data->flags != MMC_DATA_READ)
217 memcpy(aligned_buffer, data->src, trans_bytes);
218 }
219
Stefan Roese13a547f2015-06-29 14:58:09 +0200220#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
221 /*
222 * Always use this bounce-buffer when
223 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
224 */
225 is_aligned = 0;
226 start_addr = (unsigned long)aligned_buffer;
227 if (data->flags != MMC_DATA_READ)
228 memcpy(aligned_buffer, data->src, trans_bytes);
229#endif
230
Lei Wen142c8f92011-06-28 21:50:06 +0000231 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
232 mode |= SDHCI_TRNS_DMA;
233#endif
234 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
235 data->blocksize),
236 SDHCI_BLOCK_SIZE);
237 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
238 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu8e5db912015-03-23 17:57:00 -0500239 } else if (cmd->resp_type & MMC_RSP_BUSY) {
240 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wen142c8f92011-06-28 21:50:06 +0000241 }
242
243 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900244#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chung6b4026d2016-10-13 10:33:06 +0900245 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
Lei Wen5b30be02011-10-08 04:14:54 +0000246 flush_cache(start_addr, trans_bytes);
Lei Wen142c8f92011-06-28 21:50:06 +0000247#endif
248 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese42817a42015-06-29 14:58:08 +0200249 start = get_timer(0);
Lei Wen142c8f92011-06-28 21:50:06 +0000250 do {
251 stat = sdhci_readl(host, SDHCI_INT_STATUS);
252 if (stat & SDHCI_INT_ERROR)
253 break;
Lei Wen142c8f92011-06-28 21:50:06 +0000254
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900255 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
256 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
257 return 0;
258 } else {
259 printf("%s: Timeout for status update!\n",
260 __func__);
Jaehoon Chung7825d202016-07-19 16:33:36 +0900261 return -ETIMEDOUT;
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900262 }
Jaehoon Chung89237a82012-04-23 02:36:25 +0000263 }
Masahiro Yamadaa63aaa02016-07-10 00:40:22 +0900264 } while ((stat & mask) != mask);
Jaehoon Chung89237a82012-04-23 02:36:25 +0000265
Lei Wen142c8f92011-06-28 21:50:06 +0000266 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
267 sdhci_cmd_done(host, cmd);
268 sdhci_writel(host, mask, SDHCI_INT_STATUS);
269 } else
270 ret = -1;
271
272 if (!ret && data)
273 ret = sdhci_transfer_data(host, data, start_addr);
274
Tushar Behera0fba4c22012-09-20 20:31:57 +0000275 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
276 udelay(1000);
277
Lei Wen142c8f92011-06-28 21:50:06 +0000278 stat = sdhci_readl(host, SDHCI_INT_STATUS);
279 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
280 if (!ret) {
281 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
282 !is_aligned && (data->flags == MMC_DATA_READ))
283 memcpy(data->dest, aligned_buffer, trans_bytes);
284 return 0;
285 }
286
287 sdhci_reset(host, SDHCI_RESET_CMD);
288 sdhci_reset(host, SDHCI_RESET_DATA);
289 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung7825d202016-07-19 16:33:36 +0900290 return -ETIMEDOUT;
Lei Wen142c8f92011-06-28 21:50:06 +0000291 else
Jaehoon Chung7825d202016-07-19 16:33:36 +0900292 return -ECOMM;
Lei Wen142c8f92011-06-28 21:50:06 +0000293}
294
295static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
296{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200297 struct sdhci_host *host = mmc->priv;
Wenyou Yang3d734042016-09-18 09:01:22 +0800298 unsigned int div, clk = 0, timeout, reg;
Wenyou Yang09456d92015-09-22 14:59:25 +0800299
300 /* Wait max 20 ms */
301 timeout = 200;
302 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
303 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
304 if (timeout == 0) {
305 printf("%s: Timeout to wait cmd & data inhibit\n",
306 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900307 return -EBUSY;
Wenyou Yang09456d92015-09-22 14:59:25 +0800308 }
309
310 timeout--;
311 udelay(100);
312 }
Lei Wen142c8f92011-06-28 21:50:06 +0000313
Wenyou Yang09456d92015-09-22 14:59:25 +0800314 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
Siva Durga Prasad Paladugu2da51252016-02-25 12:51:50 +0530315 reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN);
Wenyou Yang09456d92015-09-22 14:59:25 +0800316 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
Lei Wen142c8f92011-06-28 21:50:06 +0000317
318 if (clock == 0)
319 return 0;
320
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900321 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang3d734042016-09-18 09:01:22 +0800322 /*
323 * Check if the Host Controller supports Programmable Clock
324 * Mode.
325 */
326 if (host->clk_mul) {
327 for (div = 1; div <= 1024; div++) {
328 if ((mmc->cfg->f_max * host->clk_mul / div)
329 <= clock)
Lei Wen142c8f92011-06-28 21:50:06 +0000330 break;
331 }
Wenyou Yang3d734042016-09-18 09:01:22 +0800332
333 /*
334 * Set Programmable Clock Mode in the Clock
335 * Control register.
336 */
337 clk = SDHCI_PROG_CLOCK_MODE;
338 div--;
339 } else {
340 /* Version 3.00 divisors must be a multiple of 2. */
341 if (mmc->cfg->f_max <= clock) {
342 div = 1;
343 } else {
344 for (div = 2;
345 div < SDHCI_MAX_DIV_SPEC_300;
346 div += 2) {
347 if ((mmc->cfg->f_max / div) <= clock)
348 break;
349 }
350 }
351 div >>= 1;
Lei Wen142c8f92011-06-28 21:50:06 +0000352 }
353 } else {
354 /* Version 2.00 divisors must be a power of 2. */
355 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200356 if ((mmc->cfg->f_max / div) <= clock)
Lei Wen142c8f92011-06-28 21:50:06 +0000357 break;
358 }
Wenyou Yang3d734042016-09-18 09:01:22 +0800359 div >>= 1;
Lei Wen142c8f92011-06-28 21:50:06 +0000360 }
Lei Wen142c8f92011-06-28 21:50:06 +0000361
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900362 if (host->ops && host->ops->set_clock)
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900363 host->ops->set_clock(host, div);
Jaehoon Chungb1929ea2012-08-30 16:24:11 +0000364
Wenyou Yang3d734042016-09-18 09:01:22 +0800365 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wen142c8f92011-06-28 21:50:06 +0000366 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
367 << SDHCI_DIVIDER_HI_SHIFT;
368 clk |= SDHCI_CLOCK_INT_EN;
369 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
370
371 /* Wait max 20 ms */
372 timeout = 20;
373 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
374 & SDHCI_CLOCK_INT_STABLE)) {
375 if (timeout == 0) {
Darwin Rambo43558132013-12-19 15:13:25 -0800376 printf("%s: Internal clock never stabilised.\n",
377 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900378 return -EBUSY;
Lei Wen142c8f92011-06-28 21:50:06 +0000379 }
380 timeout--;
381 udelay(1000);
382 }
383
384 clk |= SDHCI_CLOCK_CARD_EN;
385 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
386 return 0;
387}
388
389static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
390{
391 u8 pwr = 0;
392
393 if (power != (unsigned short)-1) {
394 switch (1 << power) {
395 case MMC_VDD_165_195:
396 pwr = SDHCI_POWER_180;
397 break;
398 case MMC_VDD_29_30:
399 case MMC_VDD_30_31:
400 pwr = SDHCI_POWER_300;
401 break;
402 case MMC_VDD_32_33:
403 case MMC_VDD_33_34:
404 pwr = SDHCI_POWER_330;
405 break;
406 }
407 }
408
409 if (pwr == 0) {
410 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
411 return;
412 }
413
414 pwr |= SDHCI_POWER_ON;
415
416 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
417}
418
Simon Glassb97f0fa2016-06-12 23:30:28 -0600419#ifdef CONFIG_DM_MMC_OPS
420static int sdhci_set_ios(struct udevice *dev)
421{
422 struct mmc *mmc = mmc_get_mmc_dev(dev);
423#else
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900424static int sdhci_set_ios(struct mmc *mmc)
Lei Wen142c8f92011-06-28 21:50:06 +0000425{
Simon Glassb97f0fa2016-06-12 23:30:28 -0600426#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000427 u32 ctrl;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200428 struct sdhci_host *host = mmc->priv;
Lei Wen142c8f92011-06-28 21:50:06 +0000429
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900430 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung46d3c032016-12-30 15:30:18 +0900431 host->ops->set_control_reg(host);
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000432
Lei Wen142c8f92011-06-28 21:50:06 +0000433 if (mmc->clock != host->clock)
434 sdhci_set_clock(mmc, mmc->clock);
435
436 /* Set bus width */
437 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
438 if (mmc->bus_width == 8) {
439 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung46e627c2013-07-19 17:44:49 +0900440 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
441 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wen142c8f92011-06-28 21:50:06 +0000442 ctrl |= SDHCI_CTRL_8BITBUS;
443 } else {
Matt Reimer9651f592015-02-19 11:22:53 -0700444 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
445 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wen142c8f92011-06-28 21:50:06 +0000446 ctrl &= ~SDHCI_CTRL_8BITBUS;
447 if (mmc->bus_width == 4)
448 ctrl |= SDHCI_CTRL_4BITBUS;
449 else
450 ctrl &= ~SDHCI_CTRL_4BITBUS;
451 }
452
453 if (mmc->clock > 26000000)
454 ctrl |= SDHCI_CTRL_HISPD;
455 else
456 ctrl &= ~SDHCI_CTRL_HISPD;
457
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000458 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
459 ctrl &= ~SDHCI_CTRL_HISPD;
460
Lei Wen142c8f92011-06-28 21:50:06 +0000461 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chungb6cd1d32016-12-30 15:30:16 +0900462
Simon Glassb97f0fa2016-06-12 23:30:28 -0600463 return 0;
Lei Wen142c8f92011-06-28 21:50:06 +0000464}
465
Jeroen Hofsteeee54c7b2014-10-08 22:57:43 +0200466static int sdhci_init(struct mmc *mmc)
Lei Wen142c8f92011-06-28 21:50:06 +0000467{
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200468 struct sdhci_host *host = mmc->priv;
Lei Wen142c8f92011-06-28 21:50:06 +0000469
Masahiro Yamadaea04d902016-08-25 16:07:34 +0900470 sdhci_reset(host, SDHCI_RESET_ALL);
471
Lei Wen142c8f92011-06-28 21:50:06 +0000472 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
473 aligned_buffer = memalign(8, 512*1024);
474 if (!aligned_buffer) {
Darwin Rambo43558132013-12-19 15:13:25 -0800475 printf("%s: Aligned buffer alloc failed!!!\n",
476 __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900477 return -ENOMEM;
Lei Wen142c8f92011-06-28 21:50:06 +0000478 }
479 }
480
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200481 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger456f34a2012-08-17 10:18:55 +0000482
Masahiro Yamadaeeb91ad2017-01-13 11:51:51 +0900483 if (host->ops && host->ops->get_cd)
Jaehoon Chung730a5952016-12-30 15:30:15 +0900484 host->ops->get_cd(host);
Joe Hershberger456f34a2012-08-17 10:18:55 +0000485
Łukasz Majewskid56a52a2013-01-11 05:08:54 +0000486 /* Enable only interrupts served by the SD controller */
Darwin Rambo43558132013-12-19 15:13:25 -0800487 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
488 SDHCI_INT_ENABLE);
Łukasz Majewskid56a52a2013-01-11 05:08:54 +0000489 /* Mask all sdhci interrupt sources */
490 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wen142c8f92011-06-28 21:50:06 +0000491
Lei Wen142c8f92011-06-28 21:50:06 +0000492 return 0;
493}
494
Simon Glassb97f0fa2016-06-12 23:30:28 -0600495#ifdef CONFIG_DM_MMC_OPS
496int sdhci_probe(struct udevice *dev)
497{
498 struct mmc *mmc = mmc_get_mmc_dev(dev);
499
500 return sdhci_init(mmc);
501}
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200502
Simon Glassb97f0fa2016-06-12 23:30:28 -0600503const struct dm_mmc_ops sdhci_ops = {
504 .send_cmd = sdhci_send_command,
505 .set_ios = sdhci_set_ios,
506};
507#else
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200508static const struct mmc_ops sdhci_ops = {
509 .send_cmd = sdhci_send_command,
510 .set_ios = sdhci_set_ios,
511 .init = sdhci_init,
512};
Simon Glassb97f0fa2016-06-12 23:30:28 -0600513#endif
Pantelis Antoniouc9e75912014-02-26 19:28:45 +0200514
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900515int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
516 u32 max_clk, u32 min_clk)
Lei Wen142c8f92011-06-28 21:50:06 +0000517{
Wenyou Yang3d734042016-09-18 09:01:22 +0800518 u32 caps, caps_1;
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900519
520 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Masahiro Yamada27bfb712016-08-25 16:07:37 +0900521
Masahiro Yamada124f6ce2016-12-07 22:10:29 +0900522#ifdef CONFIG_MMC_SDHCI_SDMA
Masahiro Yamada27bfb712016-08-25 16:07:37 +0900523 if (!(caps & SDHCI_CAN_DO_SDMA)) {
524 printf("%s: Your controller doesn't support SDMA!!\n",
525 __func__);
526 return -EINVAL;
527 }
528#endif
Jaehoon Chung6c5b3592016-09-26 08:10:01 +0900529 if (host->quirks & SDHCI_QUIRK_REG32_RW)
530 host->version =
531 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
532 else
533 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900534
535 cfg->name = host->name;
Simon Glassb0842072016-06-12 23:30:27 -0600536#ifndef CONFIG_DM_MMC_OPS
537 cfg->ops = &sdhci_ops;
Lei Wen142c8f92011-06-28 21:50:06 +0000538#endif
Lei Wen142c8f92011-06-28 21:50:06 +0000539 if (max_clk)
Simon Glassb0842072016-06-12 23:30:27 -0600540 cfg->f_max = max_clk;
Lei Wen142c8f92011-06-28 21:50:06 +0000541 else {
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900542 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glassb0842072016-06-12 23:30:27 -0600543 cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
544 SDHCI_CLOCK_BASE_SHIFT;
Lei Wen142c8f92011-06-28 21:50:06 +0000545 else
Simon Glassb0842072016-06-12 23:30:27 -0600546 cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
547 SDHCI_CLOCK_BASE_SHIFT;
548 cfg->f_max *= 1000000;
Lei Wen142c8f92011-06-28 21:50:06 +0000549 }
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900550 if (cfg->f_max == 0) {
551 printf("%s: Hardware doesn't specify base clock frequency\n",
552 __func__);
Simon Glassb0842072016-06-12 23:30:27 -0600553 return -EINVAL;
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900554 }
Lei Wen142c8f92011-06-28 21:50:06 +0000555 if (min_clk)
Simon Glassb0842072016-06-12 23:30:27 -0600556 cfg->f_min = min_clk;
Lei Wen142c8f92011-06-28 21:50:06 +0000557 else {
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900558 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glassb0842072016-06-12 23:30:27 -0600559 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
Lei Wen142c8f92011-06-28 21:50:06 +0000560 else
Simon Glassb0842072016-06-12 23:30:27 -0600561 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
Lei Wen142c8f92011-06-28 21:50:06 +0000562 }
Simon Glassb0842072016-06-12 23:30:27 -0600563 cfg->voltages = 0;
Lei Wen142c8f92011-06-28 21:50:06 +0000564 if (caps & SDHCI_CAN_VDD_330)
Simon Glassb0842072016-06-12 23:30:27 -0600565 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
Lei Wen142c8f92011-06-28 21:50:06 +0000566 if (caps & SDHCI_CAN_VDD_300)
Simon Glassb0842072016-06-12 23:30:27 -0600567 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
Lei Wen142c8f92011-06-28 21:50:06 +0000568 if (caps & SDHCI_CAN_VDD_180)
Simon Glassb0842072016-06-12 23:30:27 -0600569 cfg->voltages |= MMC_VDD_165_195;
Jaehoon Chung53889ed2012-04-23 02:36:26 +0000570
Masahiro Yamada4b338772016-08-25 16:07:36 +0900571 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
572 cfg->voltages |= host->voltages;
573
Simon Glassb0842072016-06-12 23:30:27 -0600574 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
Jaehoon Chungbc00a542016-12-30 15:30:21 +0900575
576 /* Since Host Controller Version3.0 */
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900577 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chung665152e2016-12-30 15:30:11 +0900578 if (!(caps & SDHCI_CAN_DO_8BIT))
579 cfg->host_caps &= ~MMC_MODE_8BIT;
Jaehoon Chungbc00a542016-12-30 15:30:21 +0900580
581 /* Find out whether clock multiplier is supported */
582 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
583 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
584 SDHCI_CLOCK_MUL_SHIFT;
Jagannadha Sutradharudu Teki08706be2013-05-21 15:01:36 +0530585 }
Siva Durga Prasad Paladugub0fbb492016-01-12 15:12:15 +0530586
Jaehoon Chung8a5ffbb2016-07-26 19:06:24 +0900587 if (host->host_caps)
588 cfg->host_caps |= host->host_caps;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200589
Simon Glassb0842072016-06-12 23:30:27 -0600590 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
591
592 return 0;
593}
594
Simon Glassb97f0fa2016-06-12 23:30:28 -0600595#ifdef CONFIG_BLK
596int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
597{
598 return mmc_bind(dev, mmc, cfg);
599}
600#else
Simon Glassb0842072016-06-12 23:30:27 -0600601int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
602{
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900603 int ret;
604
Masahiro Yamadada957dd2016-08-25 16:07:35 +0900605 ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
606 if (ret)
607 return ret;
Simon Glassb0842072016-06-12 23:30:27 -0600608
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200609 host->mmc = mmc_create(&host->cfg, host);
610 if (host->mmc == NULL) {
611 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chungfc6c1c62016-09-26 08:10:02 +0900612 return -ENOMEM;
Pantelis Antoniou2c850462014-03-11 19:34:20 +0200613 }
Lei Wen142c8f92011-06-28 21:50:06 +0000614
615 return 0;
616}
Simon Glassb97f0fa2016-06-12 23:30:28 -0600617#endif