Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 2 | /* |
| 3 | * clocks_am33xx.h |
| 4 | * |
| 5 | * AM33xx clock define |
| 6 | * |
Nishanth Menon | eaa39c6 | 2023-11-01 15:56:03 -0500 | [diff] [blame] | 7 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ |
Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef _CLOCKS_AM33XX_H_ |
| 11 | #define _CLOCKS_AM33XX_H_ |
| 12 | |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 13 | /* MAIN PLL Fdll supported frequencies */ |
| 14 | #define MPUPLL_M_1000 1000 |
| 15 | #define MPUPLL_M_800 800 |
| 16 | #define MPUPLL_M_720 720 |
| 17 | #define MPUPLL_M_600 600 |
Lokesh Vutla | 1bda373 | 2017-05-05 12:59:08 +0530 | [diff] [blame] | 18 | #define MPUPLL_M_500 500 |
Tom Rini | 5243707 | 2013-08-30 16:28:46 -0400 | [diff] [blame] | 19 | #define MPUPLL_M_300 300 |
| 20 | |
Heiko Schocher | b21f2ac | 2013-07-30 10:48:54 +0530 | [diff] [blame] | 21 | #define UART_RESET (0x1 << 1) |
| 22 | #define UART_CLK_RUNNING_MASK 0x1 |
| 23 | #define UART_SMART_IDLE_EN (0x1 << 0x3) |
| 24 | |
Lokesh Vutla | a82d4e1 | 2013-12-10 15:02:22 +0530 | [diff] [blame] | 25 | #define CM_DLL_CTRL_NO_OVERRIDE 0x0 |
| 26 | #define CM_DLL_READYST 0x4 |
| 27 | |
Lokesh Vutla | 6302e53 | 2017-05-05 12:59:10 +0530 | [diff] [blame] | 28 | #define NUM_OPPS 6 |
| 29 | |
Matt Porter | 57da666 | 2013-03-15 10:07:04 +0000 | [diff] [blame] | 30 | extern void enable_dmm_clocks(void); |
Tom Rini | fbb2552 | 2017-05-16 14:46:35 -0400 | [diff] [blame] | 31 | extern void enable_emif_clocks(void); |
Steve Kipisz | 5adac35 | 2013-08-14 10:51:31 -0400 | [diff] [blame] | 32 | extern const struct dpll_params dpll_core_opp100; |
| 33 | extern struct dpll_params dpll_mpu_opp100; |
Chandan Nath | 4ba3345 | 2011-10-14 02:58:23 +0000 | [diff] [blame] | 34 | |
| 35 | #endif /* endif _CLOCKS_AM33XX_H_ */ |