blob: ac7faa4cc199df175c8c0eccf9053a0e0419e399 [file] [log] [blame]
Shawn Linc0649da2021-01-15 18:01:22 +08001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Rockchip DesignWare based PCIe host controller driver
4 *
5 * Copyright (c) 2021 Rockchip, Inc.
6 */
7
Shawn Linc0649da2021-01-15 18:01:22 +08008#include <clk.h>
9#include <dm.h>
10#include <generic-phy.h>
11#include <pci.h>
12#include <power-domain.h>
13#include <reset.h>
14#include <syscon.h>
15#include <asm/arch-rockchip/clock.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060016#include <asm/global_data.h>
Shawn Linc0649da2021-01-15 18:01:22 +080017#include <asm/io.h>
18#include <asm-generic/gpio.h>
19#include <dm/device_compat.h>
Jonas Karlmana635bcd2023-08-02 19:25:51 +000020#include <linux/bitfield.h>
Shawn Linc0649da2021-01-15 18:01:22 +080021#include <linux/iopoll.h>
22#include <linux/delay.h>
23#include <power/regulator.h>
24
Neil Armstrongcf214c62021-03-25 15:49:20 +010025#include "pcie_dw_common.h"
26
Shawn Linc0649da2021-01-15 18:01:22 +080027DECLARE_GLOBAL_DATA_PTR;
28
29/**
30 * struct rk_pcie - RK DW PCIe controller state
31 *
32 * @vpcie3v3: The 3.3v power supply for slot
Shawn Linc0649da2021-01-15 18:01:22 +080033 * @apb_base: The base address of vendor regs
Shawn Linc0649da2021-01-15 18:01:22 +080034 * @rst_gpio: The #PERST signal for slot
Shawn Linc0649da2021-01-15 18:01:22 +080035 */
36struct rk_pcie {
Neil Armstrongcf214c62021-03-25 15:49:20 +010037 /* Must be first member of the struct */
38 struct pcie_dw dw;
Shawn Linc0649da2021-01-15 18:01:22 +080039 struct udevice *vpcie3v3;
Shawn Linc0649da2021-01-15 18:01:22 +080040 void *apb_base;
Shawn Linc0649da2021-01-15 18:01:22 +080041 struct phy phy;
42 struct clk_bulk clks;
Shawn Linc0649da2021-01-15 18:01:22 +080043 struct reset_ctl_bulk rsts;
44 struct gpio_desc rst_gpio;
Jon Lin793de192023-04-27 10:35:33 +030045 u32 gen;
Jonas Karlmana635bcd2023-08-02 19:25:51 +000046 u32 num_lanes;
Shawn Linc0649da2021-01-15 18:01:22 +080047};
48
49/* Parameters for the waiting for iATU enabled routine */
50#define PCIE_CLIENT_GENERAL_DEBUG 0x104
51#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
52#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
53#define PCIE_CLIENT_LTSSM_STATUS 0x300
54#define SMLH_LINKUP BIT(16)
55#define RDLH_LINKUP BIT(17)
56#define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310
57#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320
58#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324
59#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328
60#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c
61#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
62#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
63#define PCIE_CLIENT_DBF_EN 0xffff0003
64
Jon Lin97be1652023-07-22 13:30:20 +000065#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000
66
Shawn Linc0649da2021-01-15 18:01:22 +080067static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
68{
69 if ((uintptr_t)addr & (size - 1)) {
70 *val = 0;
Anand Moone4e87452021-06-05 14:38:41 +000071 return -EOPNOTSUPP;
Shawn Linc0649da2021-01-15 18:01:22 +080072 }
73
74 if (size == 4) {
75 *val = readl(addr);
76 } else if (size == 2) {
77 *val = readw(addr);
78 } else if (size == 1) {
79 *val = readb(addr);
80 } else {
81 *val = 0;
82 return -ENODEV;
83 }
84
85 return 0;
86}
87
88static int rk_pcie_write(void __iomem *addr, int size, u32 val)
89{
90 if ((uintptr_t)addr & (size - 1))
Anand Moone4e87452021-06-05 14:38:41 +000091 return -EOPNOTSUPP;
Shawn Linc0649da2021-01-15 18:01:22 +080092
93 if (size == 4)
94 writel(val, addr);
95 else if (size == 2)
96 writew(val, addr);
97 else if (size == 1)
98 writeb(val, addr);
99 else
100 return -ENODEV;
101
102 return 0;
103}
104
105static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base,
106 u32 reg, size_t size)
107{
108 int ret;
109 u32 val;
110
111 ret = rk_pcie_read(base + reg, size, &val);
112 if (ret)
Neil Armstrongcf214c62021-03-25 15:49:20 +0100113 dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
Shawn Linc0649da2021-01-15 18:01:22 +0800114
115 return val;
116}
117
118static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base,
119 u32 reg, size_t size, u32 val)
120{
121 int ret;
122
123 ret = rk_pcie_write(base + reg, size, val);
124 if (ret)
Neil Armstrongcf214c62021-03-25 15:49:20 +0100125 dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
Shawn Linc0649da2021-01-15 18:01:22 +0800126}
127
128/**
129 * rk_pcie_readl_apb() - Read vendor regs
130 *
131 * @rk_pcie: Pointer to the PCI controller state
132 * @reg: Offset of regs
133 */
134static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
135{
136 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4);
137}
138
139/**
140 * rk_pcie_writel_apb() - Write vendor regs
141 *
142 * @rk_pcie: Pointer to the PCI controller state
143 * @reg: Offset of regs
144 * @val: Value to be writen
145 */
146static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
147 u32 val)
148{
149 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val);
150}
151
Shawn Linc0649da2021-01-15 18:01:22 +0800152/**
153 * rk_pcie_configure() - Configure link capabilities and speed
154 *
155 * @rk_pcie: Pointer to the PCI controller state
Shawn Linc0649da2021-01-15 18:01:22 +0800156 *
157 * Configure the link capabilities and speed in the PCIe root complex.
158 */
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000159static void rk_pcie_configure(struct rk_pcie *pci)
Shawn Linc0649da2021-01-15 18:01:22 +0800160{
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000161 u32 val;
162
Neil Armstrongcf214c62021-03-25 15:49:20 +0100163 dw_pcie_dbi_write_enable(&pci->dw, true);
Shawn Linc0649da2021-01-15 18:01:22 +0800164
Jon Lin97be1652023-07-22 13:30:20 +0000165 /* Disable BAR 0 and BAR 1 */
166 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
167 PCI_BASE_ADDRESS_0);
168 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
169 PCI_BASE_ADDRESS_1);
170
Neil Armstrongcf214c62021-03-25 15:49:20 +0100171 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000172 TARGET_LINK_SPEED_MASK, pci->gen);
Shawn Linc0649da2021-01-15 18:01:22 +0800173
Neil Armstrongcf214c62021-03-25 15:49:20 +0100174 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000175 TARGET_LINK_SPEED_MASK, pci->gen);
Shawn Linc0649da2021-01-15 18:01:22 +0800176
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000177 /* Set the number of lanes */
178 val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
179 val &= ~PORT_LINK_FAST_LINK_MODE;
180 val |= PORT_LINK_DLL_LINK_EN;
181 val &= ~PORT_LINK_MODE_MASK;
182 switch (pci->num_lanes) {
183 case 1:
184 val |= PORT_LINK_MODE_1_LANES;
185 break;
186 case 2:
187 val |= PORT_LINK_MODE_2_LANES;
188 break;
189 case 4:
190 val |= PORT_LINK_MODE_4_LANES;
191 break;
192 default:
193 dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes);
194 goto out;
195 }
196 writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
197
198 /* Set link width speed control register */
199 val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
200 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
201 switch (pci->num_lanes) {
202 case 1:
203 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
204 break;
205 case 2:
206 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
207 break;
208 case 4:
209 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
210 break;
211 }
212 writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
213
214out:
Neil Armstrongcf214c62021-03-25 15:49:20 +0100215 dw_pcie_dbi_write_enable(&pci->dw, false);
Shawn Linc0649da2021-01-15 18:01:22 +0800216}
217
Shawn Linc0649da2021-01-15 18:01:22 +0800218static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie)
219{
220 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0,
221 PCIE_CLIENT_DBG_TRANSITION_DATA);
222 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1,
223 PCIE_CLIENT_DBG_TRANSITION_DATA);
224 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0,
225 PCIE_CLIENT_DBG_TRANSITION_DATA);
226 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1,
227 PCIE_CLIENT_DBG_TRANSITION_DATA);
228 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON,
229 PCIE_CLIENT_DBF_EN);
230}
231
232static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie)
233{
234 u32 loop;
235
236 debug("ltssm = 0x%x\n",
237 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
238 for (loop = 0; loop < 64; loop++)
239 debug("fifo_status = 0x%x\n",
240 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
241}
242
243static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie)
244{
245 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0);
246}
247
248static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie)
249{
250 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008);
251}
252
253static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie)
254{
255 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c);
256}
257
258static int is_link_up(struct rk_pcie *priv)
259{
260 u32 val;
261
262 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS);
263 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 &&
264 (val & GENMASK(5, 0)) == 0x11)
265 return 1;
266
267 return 0;
268}
269
270/**
271 * rk_pcie_link_up() - Wait for the link to come up
272 *
273 * @rk_pcie: Pointer to the PCI controller state
Shawn Linc0649da2021-01-15 18:01:22 +0800274 *
275 * Return: 1 (true) for active line and negetive (false) for no link (timeout)
276 */
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000277static int rk_pcie_link_up(struct rk_pcie *priv)
Shawn Linc0649da2021-01-15 18:01:22 +0800278{
279 int retries;
280
281 if (is_link_up(priv)) {
282 printf("PCI Link already up before configuration!\n");
283 return 1;
284 }
285
286 /* DW pre link configurations */
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000287 rk_pcie_configure(priv);
Shawn Linc0649da2021-01-15 18:01:22 +0800288
Shawn Linc0649da2021-01-15 18:01:22 +0800289 rk_pcie_disable_ltssm(priv);
290 rk_pcie_link_status_clear(priv);
291 rk_pcie_enable_debug(priv);
292
Jonas Karlman64942b72023-07-22 13:30:19 +0000293 /* Reset the device */
294 if (dm_gpio_is_valid(&priv->rst_gpio))
295 dm_gpio_set_value(&priv->rst_gpio, 0);
296
Shawn Linc0649da2021-01-15 18:01:22 +0800297 /* Enable LTSSM */
298 rk_pcie_enable_ltssm(priv);
299
Jonas Karlman64942b72023-07-22 13:30:19 +0000300 /*
301 * PCIe requires the refclk to be stable for 100ms prior to releasing
302 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI
303 * Express Card Electromechanical Specification, 1.1. However, we don't
304 * know if the refclk is coming from RC's PHY or external OSC. If it's
305 * from RC, so enabling LTSSM is the just right place to release #PERST.
306 */
307 mdelay(100);
308 if (dm_gpio_is_valid(&priv->rst_gpio))
309 dm_gpio_set_value(&priv->rst_gpio, 1);
310
311 /* Check if the link is up or not */
312 for (retries = 0; retries < 10; retries++) {
313 if (is_link_up(priv))
314 break;
315
316 mdelay(100);
317 }
Shawn Linc0649da2021-01-15 18:01:22 +0800318
Jonas Karlman64942b72023-07-22 13:30:19 +0000319 if (retries >= 10) {
320 dev_err(priv->dw.dev, "PCIe-%d Link Fail\n",
321 dev_seq(priv->dw.dev));
322 return -EIO;
Shawn Linc0649da2021-01-15 18:01:22 +0800323 }
324
Jonas Karlman64942b72023-07-22 13:30:19 +0000325 dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
326 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
327 rk_pcie_debug_dump(priv);
328 return 0;
Shawn Linc0649da2021-01-15 18:01:22 +0800329}
330
331static int rockchip_pcie_init_port(struct udevice *dev)
332{
333 int ret;
334 u32 val;
335 struct rk_pcie *priv = dev_get_priv(dev);
336
Jonas Karlman64942b72023-07-22 13:30:19 +0000337 ret = reset_assert_bulk(&priv->rsts);
338 if (ret) {
339 dev_err(dev, "failed to assert resets (ret=%d)\n", ret);
340 return ret;
341 }
342
Shawn Linc0649da2021-01-15 18:01:22 +0800343 /* Set power and maybe external ref clk input */
Jonas Karlman39993bc2023-07-22 13:30:18 +0000344 ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
345 if (ret && ret != -ENOSYS) {
346 dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
347 return ret;
Shawn Linc0649da2021-01-15 18:01:22 +0800348 }
349
Shawn Linc0649da2021-01-15 18:01:22 +0800350 ret = generic_phy_init(&priv->phy);
351 if (ret) {
352 dev_err(dev, "failed to init phy (ret=%d)\n", ret);
Jonas Karlman39993bc2023-07-22 13:30:18 +0000353 goto err_disable_regulator;
Shawn Linc0649da2021-01-15 18:01:22 +0800354 }
355
356 ret = generic_phy_power_on(&priv->phy);
357 if (ret) {
358 dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
359 goto err_exit_phy;
360 }
361
362 ret = reset_deassert_bulk(&priv->rsts);
363 if (ret) {
364 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret);
365 goto err_power_off_phy;
366 }
367
368 ret = clk_enable_bulk(&priv->clks);
369 if (ret) {
370 dev_err(dev, "failed to enable clks (ret=%d)\n", ret);
371 goto err_deassert_bulk;
372 }
373
374 /* LTSSM EN ctrl mode */
375 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL);
376 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16);
377 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val);
378
379 /* Set RC mode */
380 rk_pcie_writel_apb(priv, 0x0, 0xf00040);
Neil Armstrongcf214c62021-03-25 15:49:20 +0100381 pcie_dw_setup_host(&priv->dw);
Shawn Linc0649da2021-01-15 18:01:22 +0800382
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000383 ret = rk_pcie_link_up(priv);
Shawn Linc0649da2021-01-15 18:01:22 +0800384 if (ret < 0)
385 goto err_link_up;
386
387 return 0;
388err_link_up:
389 clk_disable_bulk(&priv->clks);
390err_deassert_bulk:
391 reset_assert_bulk(&priv->rsts);
392err_power_off_phy:
393 generic_phy_power_off(&priv->phy);
394err_exit_phy:
395 generic_phy_exit(&priv->phy);
Jonas Karlman39993bc2023-07-22 13:30:18 +0000396err_disable_regulator:
397 regulator_set_enable_if_allowed(priv->vpcie3v3, false);
Shawn Linc0649da2021-01-15 18:01:22 +0800398
399 return ret;
400}
401
402static int rockchip_pcie_parse_dt(struct udevice *dev)
403{
404 struct rk_pcie *priv = dev_get_priv(dev);
405 int ret;
406
Johan Jonker5ff88122023-03-13 01:31:49 +0100407 priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0);
Neil Armstrongcf214c62021-03-25 15:49:20 +0100408 if (!priv->dw.dbi_base)
Johan Jonker5ff88122023-03-13 01:31:49 +0100409 return -EINVAL;
Shawn Linc0649da2021-01-15 18:01:22 +0800410
Neil Armstrongcf214c62021-03-25 15:49:20 +0100411 dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base);
Shawn Linc0649da2021-01-15 18:01:22 +0800412
Johan Jonker5ff88122023-03-13 01:31:49 +0100413 priv->apb_base = dev_read_addr_index_ptr(dev, 1);
Shawn Linc0649da2021-01-15 18:01:22 +0800414 if (!priv->apb_base)
Johan Jonker5ff88122023-03-13 01:31:49 +0100415 return -EINVAL;
Shawn Linc0649da2021-01-15 18:01:22 +0800416
417 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
418
Jonas Karlman8746d9c2023-07-22 13:30:16 +0000419 priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2,
420 &priv->dw.cfg_size);
421 if (!priv->dw.cfg_base)
422 return -EINVAL;
423
424 dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base);
425
Shawn Linc0649da2021-01-15 18:01:22 +0800426 ret = gpio_request_by_name(dev, "reset-gpios", 0,
427 &priv->rst_gpio, GPIOD_IS_OUT);
428 if (ret) {
429 dev_err(dev, "failed to find reset-gpios property\n");
430 return ret;
431 }
432
433 ret = reset_get_bulk(dev, &priv->rsts);
434 if (ret) {
435 dev_err(dev, "Can't get reset: %d\n", ret);
Eugen Hristev32a51032023-04-13 17:11:03 +0300436 goto rockchip_pcie_parse_dt_err_reset_get_bulk;
Shawn Linc0649da2021-01-15 18:01:22 +0800437 }
438
439 ret = clk_get_bulk(dev, &priv->clks);
440 if (ret) {
441 dev_err(dev, "Can't get clock: %d\n", ret);
Eugen Hristev32a51032023-04-13 17:11:03 +0300442 goto rockchip_pcie_parse_dt_err_clk_get_bulk;
Shawn Linc0649da2021-01-15 18:01:22 +0800443 }
444
445 ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
446 &priv->vpcie3v3);
447 if (ret && ret != -ENOENT) {
448 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
Eugen Hristev32a51032023-04-13 17:11:03 +0300449 goto rockchip_pcie_parse_dt_err_supply_regulator;
Shawn Linc0649da2021-01-15 18:01:22 +0800450 }
451
452 ret = generic_phy_get_by_index(dev, 0, &priv->phy);
453 if (ret) {
454 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret);
Eugen Hristev32a51032023-04-13 17:11:03 +0300455 goto rockchip_pcie_parse_dt_err_phy_get_by_index;
Shawn Linc0649da2021-01-15 18:01:22 +0800456 }
457
Jon Lin793de192023-04-27 10:35:33 +0300458 priv->gen = dev_read_u32_default(dev, "max-link-speed",
459 LINK_SPEED_GEN_3);
460
Jonas Karlmana635bcd2023-08-02 19:25:51 +0000461 priv->num_lanes = dev_read_u32_default(dev, "num-lanes", 1);
462
Shawn Linc0649da2021-01-15 18:01:22 +0800463 return 0;
Eugen Hristev32a51032023-04-13 17:11:03 +0300464
465rockchip_pcie_parse_dt_err_phy_get_by_index:
466 /* regulators don't need release */
467rockchip_pcie_parse_dt_err_supply_regulator:
468 clk_release_bulk(&priv->clks);
469rockchip_pcie_parse_dt_err_clk_get_bulk:
470 reset_release_bulk(&priv->rsts);
471rockchip_pcie_parse_dt_err_reset_get_bulk:
472 dm_gpio_free(dev, &priv->rst_gpio);
473 return ret;
Shawn Linc0649da2021-01-15 18:01:22 +0800474}
475
476/**
477 * rockchip_pcie_probe() - Probe the PCIe bus for active link
478 *
479 * @dev: A pointer to the device being operated on
480 *
481 * Probe for an active link on the PCIe bus and configure the controller
482 * to enable this port.
483 *
484 * Return: 0 on success, else -ENODEV
485 */
486static int rockchip_pcie_probe(struct udevice *dev)
487{
488 struct rk_pcie *priv = dev_get_priv(dev);
489 struct udevice *ctlr = pci_get_controller(dev);
490 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
Neil Armstrongcf214c62021-03-25 15:49:20 +0100491 int ret = 0;
Shawn Linc0649da2021-01-15 18:01:22 +0800492
Neil Armstrongcf214c62021-03-25 15:49:20 +0100493 priv->dw.first_busno = dev_seq(dev);
494 priv->dw.dev = dev;
Shawn Linc0649da2021-01-15 18:01:22 +0800495
496 ret = rockchip_pcie_parse_dt(dev);
497 if (ret)
498 return ret;
499
500 ret = rockchip_pcie_init_port(dev);
501 if (ret)
Eugen Hristev32a51032023-04-13 17:11:03 +0300502 goto rockchip_pcie_probe_err_init_port;
Shawn Linc0649da2021-01-15 18:01:22 +0800503
504 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
Neil Armstrongcf214c62021-03-25 15:49:20 +0100505 dev_seq(dev), pcie_dw_get_link_speed(&priv->dw),
506 pcie_dw_get_link_width(&priv->dw),
Shawn Linc0649da2021-01-15 18:01:22 +0800507 hose->first_busno);
508
Eugen Hristev32a51032023-04-13 17:11:03 +0300509 ret = pcie_dw_prog_outbound_atu_unroll(&priv->dw,
510 PCIE_ATU_REGION_INDEX0,
511 PCIE_ATU_TYPE_MEM,
512 priv->dw.mem.phys_start,
513 priv->dw.mem.bus_start,
514 priv->dw.mem.size);
515 if (!ret)
516 return ret;
517
518rockchip_pcie_probe_err_init_port:
519 clk_release_bulk(&priv->clks);
520 reset_release_bulk(&priv->rsts);
521 dm_gpio_free(dev, &priv->rst_gpio);
Shawn Linc0649da2021-01-15 18:01:22 +0800522
Eugen Hristev32a51032023-04-13 17:11:03 +0300523 return ret;
Shawn Linc0649da2021-01-15 18:01:22 +0800524}
525
526static const struct dm_pci_ops rockchip_pcie_ops = {
Neil Armstrongcf214c62021-03-25 15:49:20 +0100527 .read_config = pcie_dw_read_config,
528 .write_config = pcie_dw_write_config,
Shawn Linc0649da2021-01-15 18:01:22 +0800529};
530
531static const struct udevice_id rockchip_pcie_ids[] = {
532 { .compatible = "rockchip,rk3568-pcie" },
Jon Lin2bdea352023-04-27 10:35:32 +0300533 { .compatible = "rockchip,rk3588-pcie" },
Shawn Linc0649da2021-01-15 18:01:22 +0800534 { }
535};
536
537U_BOOT_DRIVER(rockchip_dw_pcie) = {
538 .name = "pcie_dw_rockchip",
539 .id = UCLASS_PCI,
540 .of_match = rockchip_pcie_ids,
541 .ops = &rockchip_pcie_ops,
542 .probe = rockchip_pcie_probe,
543 .priv_auto = sizeof(struct rk_pcie),
544};