Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Rockchip DesignWare based PCIe host controller driver |
| 4 | * |
| 5 | * Copyright (c) 2021 Rockchip, Inc. |
| 6 | */ |
| 7 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 8 | #include <clk.h> |
| 9 | #include <dm.h> |
| 10 | #include <generic-phy.h> |
| 11 | #include <pci.h> |
| 12 | #include <power-domain.h> |
| 13 | #include <reset.h> |
| 14 | #include <syscon.h> |
| 15 | #include <asm/arch-rockchip/clock.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 16 | #include <asm/global_data.h> |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 17 | #include <asm/io.h> |
| 18 | #include <asm-generic/gpio.h> |
| 19 | #include <dm/device_compat.h> |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 20 | #include <linux/bitfield.h> |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 21 | #include <linux/iopoll.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <power/regulator.h> |
| 24 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 25 | #include "pcie_dw_common.h" |
| 26 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | /** |
| 30 | * struct rk_pcie - RK DW PCIe controller state |
| 31 | * |
| 32 | * @vpcie3v3: The 3.3v power supply for slot |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 33 | * @apb_base: The base address of vendor regs |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 34 | * @rst_gpio: The #PERST signal for slot |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 35 | */ |
| 36 | struct rk_pcie { |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 37 | /* Must be first member of the struct */ |
| 38 | struct pcie_dw dw; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 39 | struct udevice *vpcie3v3; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 40 | void *apb_base; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 41 | struct phy phy; |
| 42 | struct clk_bulk clks; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 43 | struct reset_ctl_bulk rsts; |
| 44 | struct gpio_desc rst_gpio; |
Jon Lin | 793de19 | 2023-04-27 10:35:33 +0300 | [diff] [blame] | 45 | u32 gen; |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 46 | u32 num_lanes; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 47 | }; |
| 48 | |
| 49 | /* Parameters for the waiting for iATU enabled routine */ |
| 50 | #define PCIE_CLIENT_GENERAL_DEBUG 0x104 |
| 51 | #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 |
| 52 | #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) |
| 53 | #define PCIE_CLIENT_LTSSM_STATUS 0x300 |
| 54 | #define SMLH_LINKUP BIT(16) |
| 55 | #define RDLH_LINKUP BIT(17) |
| 56 | #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 |
| 57 | #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 |
| 58 | #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 |
| 59 | #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 |
| 60 | #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c |
| 61 | #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 |
| 62 | #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 |
| 63 | #define PCIE_CLIENT_DBF_EN 0xffff0003 |
| 64 | |
Jon Lin | 97be165 | 2023-07-22 13:30:20 +0000 | [diff] [blame] | 65 | #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 |
| 66 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 67 | static int rk_pcie_read(void __iomem *addr, int size, u32 *val) |
| 68 | { |
| 69 | if ((uintptr_t)addr & (size - 1)) { |
| 70 | *val = 0; |
Anand Moon | e4e8745 | 2021-06-05 14:38:41 +0000 | [diff] [blame] | 71 | return -EOPNOTSUPP; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | if (size == 4) { |
| 75 | *val = readl(addr); |
| 76 | } else if (size == 2) { |
| 77 | *val = readw(addr); |
| 78 | } else if (size == 1) { |
| 79 | *val = readb(addr); |
| 80 | } else { |
| 81 | *val = 0; |
| 82 | return -ENODEV; |
| 83 | } |
| 84 | |
| 85 | return 0; |
| 86 | } |
| 87 | |
| 88 | static int rk_pcie_write(void __iomem *addr, int size, u32 val) |
| 89 | { |
| 90 | if ((uintptr_t)addr & (size - 1)) |
Anand Moon | e4e8745 | 2021-06-05 14:38:41 +0000 | [diff] [blame] | 91 | return -EOPNOTSUPP; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 92 | |
| 93 | if (size == 4) |
| 94 | writel(val, addr); |
| 95 | else if (size == 2) |
| 96 | writew(val, addr); |
| 97 | else if (size == 1) |
| 98 | writeb(val, addr); |
| 99 | else |
| 100 | return -ENODEV; |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
| 105 | static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, |
| 106 | u32 reg, size_t size) |
| 107 | { |
| 108 | int ret; |
| 109 | u32 val; |
| 110 | |
| 111 | ret = rk_pcie_read(base + reg, size, &val); |
| 112 | if (ret) |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 113 | dev_err(rk_pcie->dw.dev, "Read APB address failed\n"); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 114 | |
| 115 | return val; |
| 116 | } |
| 117 | |
| 118 | static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, |
| 119 | u32 reg, size_t size, u32 val) |
| 120 | { |
| 121 | int ret; |
| 122 | |
| 123 | ret = rk_pcie_write(base + reg, size, val); |
| 124 | if (ret) |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 125 | dev_err(rk_pcie->dw.dev, "Write APB address failed\n"); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | /** |
| 129 | * rk_pcie_readl_apb() - Read vendor regs |
| 130 | * |
| 131 | * @rk_pcie: Pointer to the PCI controller state |
| 132 | * @reg: Offset of regs |
| 133 | */ |
| 134 | static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) |
| 135 | { |
| 136 | return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); |
| 137 | } |
| 138 | |
| 139 | /** |
| 140 | * rk_pcie_writel_apb() - Write vendor regs |
| 141 | * |
| 142 | * @rk_pcie: Pointer to the PCI controller state |
| 143 | * @reg: Offset of regs |
| 144 | * @val: Value to be writen |
| 145 | */ |
| 146 | static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, |
| 147 | u32 val) |
| 148 | { |
| 149 | __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); |
| 150 | } |
| 151 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 152 | /** |
| 153 | * rk_pcie_configure() - Configure link capabilities and speed |
| 154 | * |
| 155 | * @rk_pcie: Pointer to the PCI controller state |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 156 | * |
| 157 | * Configure the link capabilities and speed in the PCIe root complex. |
| 158 | */ |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 159 | static void rk_pcie_configure(struct rk_pcie *pci) |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 160 | { |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 161 | u32 val; |
| 162 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 163 | dw_pcie_dbi_write_enable(&pci->dw, true); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 164 | |
Jon Lin | 97be165 | 2023-07-22 13:30:20 +0000 | [diff] [blame] | 165 | /* Disable BAR 0 and BAR 1 */ |
| 166 | writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + |
| 167 | PCI_BASE_ADDRESS_0); |
| 168 | writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + |
| 169 | PCI_BASE_ADDRESS_1); |
| 170 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 171 | clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY, |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 172 | TARGET_LINK_SPEED_MASK, pci->gen); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 173 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 174 | clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2, |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 175 | TARGET_LINK_SPEED_MASK, pci->gen); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 176 | |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 177 | /* Set the number of lanes */ |
| 178 | val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL); |
| 179 | val &= ~PORT_LINK_FAST_LINK_MODE; |
| 180 | val |= PORT_LINK_DLL_LINK_EN; |
| 181 | val &= ~PORT_LINK_MODE_MASK; |
| 182 | switch (pci->num_lanes) { |
| 183 | case 1: |
| 184 | val |= PORT_LINK_MODE_1_LANES; |
| 185 | break; |
| 186 | case 2: |
| 187 | val |= PORT_LINK_MODE_2_LANES; |
| 188 | break; |
| 189 | case 4: |
| 190 | val |= PORT_LINK_MODE_4_LANES; |
| 191 | break; |
| 192 | default: |
| 193 | dev_err(pci->dw.dev, "num-lanes %u: invalid value\n", pci->num_lanes); |
| 194 | goto out; |
| 195 | } |
| 196 | writel(val, pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL); |
| 197 | |
| 198 | /* Set link width speed control register */ |
| 199 | val = readl(pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); |
| 200 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
| 201 | switch (pci->num_lanes) { |
| 202 | case 1: |
| 203 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; |
| 204 | break; |
| 205 | case 2: |
| 206 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; |
| 207 | break; |
| 208 | case 4: |
| 209 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; |
| 210 | break; |
| 211 | } |
| 212 | writel(val, pci->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); |
| 213 | |
| 214 | out: |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 215 | dw_pcie_dbi_write_enable(&pci->dw, false); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 216 | } |
| 217 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 218 | static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) |
| 219 | { |
| 220 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, |
| 221 | PCIE_CLIENT_DBG_TRANSITION_DATA); |
| 222 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, |
| 223 | PCIE_CLIENT_DBG_TRANSITION_DATA); |
| 224 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, |
| 225 | PCIE_CLIENT_DBG_TRANSITION_DATA); |
| 226 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, |
| 227 | PCIE_CLIENT_DBG_TRANSITION_DATA); |
| 228 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, |
| 229 | PCIE_CLIENT_DBF_EN); |
| 230 | } |
| 231 | |
| 232 | static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) |
| 233 | { |
| 234 | u32 loop; |
| 235 | |
| 236 | debug("ltssm = 0x%x\n", |
| 237 | rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); |
| 238 | for (loop = 0; loop < 64; loop++) |
| 239 | debug("fifo_status = 0x%x\n", |
| 240 | rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); |
| 241 | } |
| 242 | |
| 243 | static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) |
| 244 | { |
| 245 | rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); |
| 246 | } |
| 247 | |
| 248 | static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) |
| 249 | { |
| 250 | rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); |
| 251 | } |
| 252 | |
| 253 | static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) |
| 254 | { |
| 255 | rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); |
| 256 | } |
| 257 | |
| 258 | static int is_link_up(struct rk_pcie *priv) |
| 259 | { |
| 260 | u32 val; |
| 261 | |
| 262 | val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); |
| 263 | if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && |
| 264 | (val & GENMASK(5, 0)) == 0x11) |
| 265 | return 1; |
| 266 | |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | /** |
| 271 | * rk_pcie_link_up() - Wait for the link to come up |
| 272 | * |
| 273 | * @rk_pcie: Pointer to the PCI controller state |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 274 | * |
| 275 | * Return: 1 (true) for active line and negetive (false) for no link (timeout) |
| 276 | */ |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 277 | static int rk_pcie_link_up(struct rk_pcie *priv) |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 278 | { |
| 279 | int retries; |
| 280 | |
| 281 | if (is_link_up(priv)) { |
| 282 | printf("PCI Link already up before configuration!\n"); |
| 283 | return 1; |
| 284 | } |
| 285 | |
| 286 | /* DW pre link configurations */ |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 287 | rk_pcie_configure(priv); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 288 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 289 | rk_pcie_disable_ltssm(priv); |
| 290 | rk_pcie_link_status_clear(priv); |
| 291 | rk_pcie_enable_debug(priv); |
| 292 | |
Jonas Karlman | 64942b7 | 2023-07-22 13:30:19 +0000 | [diff] [blame] | 293 | /* Reset the device */ |
| 294 | if (dm_gpio_is_valid(&priv->rst_gpio)) |
| 295 | dm_gpio_set_value(&priv->rst_gpio, 0); |
| 296 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 297 | /* Enable LTSSM */ |
| 298 | rk_pcie_enable_ltssm(priv); |
| 299 | |
Jonas Karlman | 64942b7 | 2023-07-22 13:30:19 +0000 | [diff] [blame] | 300 | /* |
| 301 | * PCIe requires the refclk to be stable for 100ms prior to releasing |
| 302 | * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI |
| 303 | * Express Card Electromechanical Specification, 1.1. However, we don't |
| 304 | * know if the refclk is coming from RC's PHY or external OSC. If it's |
| 305 | * from RC, so enabling LTSSM is the just right place to release #PERST. |
| 306 | */ |
| 307 | mdelay(100); |
| 308 | if (dm_gpio_is_valid(&priv->rst_gpio)) |
| 309 | dm_gpio_set_value(&priv->rst_gpio, 1); |
| 310 | |
| 311 | /* Check if the link is up or not */ |
| 312 | for (retries = 0; retries < 10; retries++) { |
| 313 | if (is_link_up(priv)) |
| 314 | break; |
| 315 | |
| 316 | mdelay(100); |
| 317 | } |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 318 | |
Jonas Karlman | 64942b7 | 2023-07-22 13:30:19 +0000 | [diff] [blame] | 319 | if (retries >= 10) { |
| 320 | dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", |
| 321 | dev_seq(priv->dw.dev)); |
| 322 | return -EIO; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 323 | } |
| 324 | |
Jonas Karlman | 64942b7 | 2023-07-22 13:30:19 +0000 | [diff] [blame] | 325 | dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n", |
| 326 | rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); |
| 327 | rk_pcie_debug_dump(priv); |
| 328 | return 0; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 329 | } |
| 330 | |
| 331 | static int rockchip_pcie_init_port(struct udevice *dev) |
| 332 | { |
| 333 | int ret; |
| 334 | u32 val; |
| 335 | struct rk_pcie *priv = dev_get_priv(dev); |
| 336 | |
Jonas Karlman | 64942b7 | 2023-07-22 13:30:19 +0000 | [diff] [blame] | 337 | ret = reset_assert_bulk(&priv->rsts); |
| 338 | if (ret) { |
| 339 | dev_err(dev, "failed to assert resets (ret=%d)\n", ret); |
| 340 | return ret; |
| 341 | } |
| 342 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 343 | /* Set power and maybe external ref clk input */ |
Jonas Karlman | 39993bc | 2023-07-22 13:30:18 +0000 | [diff] [blame] | 344 | ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true); |
| 345 | if (ret && ret != -ENOSYS) { |
| 346 | dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret); |
| 347 | return ret; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 348 | } |
| 349 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 350 | ret = generic_phy_init(&priv->phy); |
| 351 | if (ret) { |
| 352 | dev_err(dev, "failed to init phy (ret=%d)\n", ret); |
Jonas Karlman | 39993bc | 2023-07-22 13:30:18 +0000 | [diff] [blame] | 353 | goto err_disable_regulator; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | ret = generic_phy_power_on(&priv->phy); |
| 357 | if (ret) { |
| 358 | dev_err(dev, "failed to power on phy (ret=%d)\n", ret); |
| 359 | goto err_exit_phy; |
| 360 | } |
| 361 | |
| 362 | ret = reset_deassert_bulk(&priv->rsts); |
| 363 | if (ret) { |
| 364 | dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); |
| 365 | goto err_power_off_phy; |
| 366 | } |
| 367 | |
| 368 | ret = clk_enable_bulk(&priv->clks); |
| 369 | if (ret) { |
| 370 | dev_err(dev, "failed to enable clks (ret=%d)\n", ret); |
| 371 | goto err_deassert_bulk; |
| 372 | } |
| 373 | |
| 374 | /* LTSSM EN ctrl mode */ |
| 375 | val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); |
| 376 | val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); |
| 377 | rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); |
| 378 | |
| 379 | /* Set RC mode */ |
| 380 | rk_pcie_writel_apb(priv, 0x0, 0xf00040); |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 381 | pcie_dw_setup_host(&priv->dw); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 382 | |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 383 | ret = rk_pcie_link_up(priv); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 384 | if (ret < 0) |
| 385 | goto err_link_up; |
| 386 | |
| 387 | return 0; |
| 388 | err_link_up: |
| 389 | clk_disable_bulk(&priv->clks); |
| 390 | err_deassert_bulk: |
| 391 | reset_assert_bulk(&priv->rsts); |
| 392 | err_power_off_phy: |
| 393 | generic_phy_power_off(&priv->phy); |
| 394 | err_exit_phy: |
| 395 | generic_phy_exit(&priv->phy); |
Jonas Karlman | 39993bc | 2023-07-22 13:30:18 +0000 | [diff] [blame] | 396 | err_disable_regulator: |
| 397 | regulator_set_enable_if_allowed(priv->vpcie3v3, false); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 398 | |
| 399 | return ret; |
| 400 | } |
| 401 | |
| 402 | static int rockchip_pcie_parse_dt(struct udevice *dev) |
| 403 | { |
| 404 | struct rk_pcie *priv = dev_get_priv(dev); |
| 405 | int ret; |
| 406 | |
Johan Jonker | 5ff8812 | 2023-03-13 01:31:49 +0100 | [diff] [blame] | 407 | priv->dw.dbi_base = dev_read_addr_index_ptr(dev, 0); |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 408 | if (!priv->dw.dbi_base) |
Johan Jonker | 5ff8812 | 2023-03-13 01:31:49 +0100 | [diff] [blame] | 409 | return -EINVAL; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 410 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 411 | dev_dbg(dev, "DBI address is 0x%p\n", priv->dw.dbi_base); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 412 | |
Johan Jonker | 5ff8812 | 2023-03-13 01:31:49 +0100 | [diff] [blame] | 413 | priv->apb_base = dev_read_addr_index_ptr(dev, 1); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 414 | if (!priv->apb_base) |
Johan Jonker | 5ff8812 | 2023-03-13 01:31:49 +0100 | [diff] [blame] | 415 | return -EINVAL; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 416 | |
| 417 | dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); |
| 418 | |
Jonas Karlman | 8746d9c | 2023-07-22 13:30:16 +0000 | [diff] [blame] | 419 | priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2, |
| 420 | &priv->dw.cfg_size); |
| 421 | if (!priv->dw.cfg_base) |
| 422 | return -EINVAL; |
| 423 | |
| 424 | dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base); |
| 425 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 426 | ret = gpio_request_by_name(dev, "reset-gpios", 0, |
| 427 | &priv->rst_gpio, GPIOD_IS_OUT); |
| 428 | if (ret) { |
| 429 | dev_err(dev, "failed to find reset-gpios property\n"); |
| 430 | return ret; |
| 431 | } |
| 432 | |
| 433 | ret = reset_get_bulk(dev, &priv->rsts); |
| 434 | if (ret) { |
| 435 | dev_err(dev, "Can't get reset: %d\n", ret); |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 436 | goto rockchip_pcie_parse_dt_err_reset_get_bulk; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | ret = clk_get_bulk(dev, &priv->clks); |
| 440 | if (ret) { |
| 441 | dev_err(dev, "Can't get clock: %d\n", ret); |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 442 | goto rockchip_pcie_parse_dt_err_clk_get_bulk; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 443 | } |
| 444 | |
| 445 | ret = device_get_supply_regulator(dev, "vpcie3v3-supply", |
| 446 | &priv->vpcie3v3); |
| 447 | if (ret && ret != -ENOENT) { |
| 448 | dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 449 | goto rockchip_pcie_parse_dt_err_supply_regulator; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | ret = generic_phy_get_by_index(dev, 0, &priv->phy); |
| 453 | if (ret) { |
| 454 | dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 455 | goto rockchip_pcie_parse_dt_err_phy_get_by_index; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 456 | } |
| 457 | |
Jon Lin | 793de19 | 2023-04-27 10:35:33 +0300 | [diff] [blame] | 458 | priv->gen = dev_read_u32_default(dev, "max-link-speed", |
| 459 | LINK_SPEED_GEN_3); |
| 460 | |
Jonas Karlman | a635bcd | 2023-08-02 19:25:51 +0000 | [diff] [blame] | 461 | priv->num_lanes = dev_read_u32_default(dev, "num-lanes", 1); |
| 462 | |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 463 | return 0; |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 464 | |
| 465 | rockchip_pcie_parse_dt_err_phy_get_by_index: |
| 466 | /* regulators don't need release */ |
| 467 | rockchip_pcie_parse_dt_err_supply_regulator: |
| 468 | clk_release_bulk(&priv->clks); |
| 469 | rockchip_pcie_parse_dt_err_clk_get_bulk: |
| 470 | reset_release_bulk(&priv->rsts); |
| 471 | rockchip_pcie_parse_dt_err_reset_get_bulk: |
| 472 | dm_gpio_free(dev, &priv->rst_gpio); |
| 473 | return ret; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 474 | } |
| 475 | |
| 476 | /** |
| 477 | * rockchip_pcie_probe() - Probe the PCIe bus for active link |
| 478 | * |
| 479 | * @dev: A pointer to the device being operated on |
| 480 | * |
| 481 | * Probe for an active link on the PCIe bus and configure the controller |
| 482 | * to enable this port. |
| 483 | * |
| 484 | * Return: 0 on success, else -ENODEV |
| 485 | */ |
| 486 | static int rockchip_pcie_probe(struct udevice *dev) |
| 487 | { |
| 488 | struct rk_pcie *priv = dev_get_priv(dev); |
| 489 | struct udevice *ctlr = pci_get_controller(dev); |
| 490 | struct pci_controller *hose = dev_get_uclass_priv(ctlr); |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 491 | int ret = 0; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 492 | |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 493 | priv->dw.first_busno = dev_seq(dev); |
| 494 | priv->dw.dev = dev; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 495 | |
| 496 | ret = rockchip_pcie_parse_dt(dev); |
| 497 | if (ret) |
| 498 | return ret; |
| 499 | |
| 500 | ret = rockchip_pcie_init_port(dev); |
| 501 | if (ret) |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 502 | goto rockchip_pcie_probe_err_init_port; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 503 | |
| 504 | dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 505 | dev_seq(dev), pcie_dw_get_link_speed(&priv->dw), |
| 506 | pcie_dw_get_link_width(&priv->dw), |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 507 | hose->first_busno); |
| 508 | |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 509 | ret = pcie_dw_prog_outbound_atu_unroll(&priv->dw, |
| 510 | PCIE_ATU_REGION_INDEX0, |
| 511 | PCIE_ATU_TYPE_MEM, |
| 512 | priv->dw.mem.phys_start, |
| 513 | priv->dw.mem.bus_start, |
| 514 | priv->dw.mem.size); |
| 515 | if (!ret) |
| 516 | return ret; |
| 517 | |
| 518 | rockchip_pcie_probe_err_init_port: |
| 519 | clk_release_bulk(&priv->clks); |
| 520 | reset_release_bulk(&priv->rsts); |
| 521 | dm_gpio_free(dev, &priv->rst_gpio); |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 522 | |
Eugen Hristev | 32a5103 | 2023-04-13 17:11:03 +0300 | [diff] [blame] | 523 | return ret; |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 524 | } |
| 525 | |
| 526 | static const struct dm_pci_ops rockchip_pcie_ops = { |
Neil Armstrong | cf214c6 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 527 | .read_config = pcie_dw_read_config, |
| 528 | .write_config = pcie_dw_write_config, |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 529 | }; |
| 530 | |
| 531 | static const struct udevice_id rockchip_pcie_ids[] = { |
| 532 | { .compatible = "rockchip,rk3568-pcie" }, |
Jon Lin | 2bdea35 | 2023-04-27 10:35:32 +0300 | [diff] [blame] | 533 | { .compatible = "rockchip,rk3588-pcie" }, |
Shawn Lin | c0649da | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 534 | { } |
| 535 | }; |
| 536 | |
| 537 | U_BOOT_DRIVER(rockchip_dw_pcie) = { |
| 538 | .name = "pcie_dw_rockchip", |
| 539 | .id = UCLASS_PCI, |
| 540 | .of_match = rockchip_pcie_ids, |
| 541 | .ops = &rockchip_pcie_ops, |
| 542 | .probe = rockchip_pcie_probe, |
| 543 | .priv_auto = sizeof(struct rk_pcie), |
| 544 | }; |