| commit | a635bcd32be89d086ebf8dc62c49f3206a72e1e9 | [log] [tgz] |
|---|---|---|
| author | Jonas Karlman <jonas@kwiboo.se> | Wed Aug 02 19:25:51 2023 +0000 |
| committer | Kever Yang <kever.yang@rock-chips.com> | Sat Oct 07 10:23:12 2023 +0800 |
| tree | f38c0edb9ecb28236bf6903f73988be18d96c66a | |
| parent | a3e88ef121ff32f3d12fbec4bbab69bd05ba0ec7 [diff] |
pci: pcie_dw_rockchip: Configure number of lanes and link width speed Set number of lanes and link width speed control register based on the num-lanes property. Code imported almost 1:1 from dw_pcie_setup in mainline linux. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>