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git01.mediatek.com / filogic / uboot / edae366c8ceca91195babf90f78e9dd5a3716aec / . / arch / powerpc / include / asm / fsl_serdes.h
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Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]2/*
3 * Copyright 2010 Freescale Semiconductor, Inc.
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]4 */
5
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]6#ifndef __FSL_SERDES_H
7#define __FSL_SERDES_H
8
9#include <config.h>
10
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]11enum srds_prtcl {
Hou Zhiqiangb435ae92016-08-02 19:03:22 +0800[diff] [blame]12 /*
13 * Nobody will check whether the device 'NONE' has been configured,
14 * So use it to indicate if the serdes_prtcl_map has been initialized.
15 */
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]16 NONE = 0,
17 PCIE1,
18 PCIE2,
19 PCIE3,
20 PCIE4,
21 SATA1,
22 SATA2,
23 SRIO1,
24 SRIO2,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]25 SGMII_FM1_DTSEC1,
26 SGMII_FM1_DTSEC2,
27 SGMII_FM1_DTSEC3,
28 SGMII_FM1_DTSEC4,
29 SGMII_FM1_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]30 SGMII_FM1_DTSEC6,
31 SGMII_FM1_DTSEC9,
32 SGMII_FM1_DTSEC10,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]33 SGMII_FM2_DTSEC1,
34 SGMII_FM2_DTSEC2,
35 SGMII_FM2_DTSEC3,
36 SGMII_FM2_DTSEC4,
Timur Tabi7920fb12012-08-14 06:47:21 +0000[diff] [blame]37 SGMII_FM2_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]38 SGMII_FM2_DTSEC6,
39 SGMII_FM2_DTSEC9,
40 SGMII_FM2_DTSEC10,
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]41 SGMII_TSEC1,
42 SGMII_TSEC2,
43 SGMII_TSEC3,
44 SGMII_TSEC4,
45 XAUI_FM1,
46 XAUI_FM2,
47 AURORA,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]48 CPRI1,
49 CPRI2,
50 CPRI3,
51 CPRI4,
52 CPRI5,
53 CPRI6,
54 CPRI7,
55 CPRI8,
56 XAUI_FM1_MAC9,
57 XAUI_FM1_MAC10,
58 XAUI_FM2_MAC9,
59 XAUI_FM2_MAC10,
60 HIGIG_FM1_MAC9,
61 HIGIG_FM1_MAC10,
62 HIGIG_FM2_MAC9,
63 HIGIG_FM2_MAC10,
64 QSGMII_FM1_A, /* A indicates MACs 1-4 */
65 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
66 QSGMII_FM2_A,
67 QSGMII_FM2_B,
Shengzhou Liu4227e492013-11-22 17:39:09 +0800[diff] [blame]68 XFI_FM1_MAC1,
69 XFI_FM1_MAC2,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]70 XFI_FM1_MAC9,
71 XFI_FM1_MAC10,
72 XFI_FM2_MAC9,
73 XFI_FM2_MAC10,
74 INTERLAKEN,
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +0530[diff] [blame]75 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]76 QSGMII_SW1_B,
Shengzhou Liu95403682014-10-23 17:20:57 +0800[diff] [blame]77 SGMII_2500_FM1_DTSEC1,
78 SGMII_2500_FM1_DTSEC2,
79 SGMII_2500_FM1_DTSEC3,
80 SGMII_2500_FM1_DTSEC4,
81 SGMII_2500_FM1_DTSEC5,
82 SGMII_2500_FM1_DTSEC6,
83 SGMII_2500_FM1_DTSEC9,
84 SGMII_2500_FM1_DTSEC10,
85 SGMII_2500_FM2_DTSEC1,
86 SGMII_2500_FM2_DTSEC2,
87 SGMII_2500_FM2_DTSEC3,
88 SGMII_2500_FM2_DTSEC4,
89 SGMII_2500_FM2_DTSEC5,
90 SGMII_2500_FM2_DTSEC6,
91 SGMII_2500_FM2_DTSEC9,
92 SGMII_2500_FM2_DTSEC10,
Codrin Ciubotariud3904782015-01-12 14:08:31 +0200[diff] [blame]93 SGMII_SW1_MAC1,
94 SGMII_SW1_MAC2,
95 SGMII_SW1_MAC3,
96 SGMII_SW1_MAC4,
97 SGMII_SW1_MAC5,
98 SGMII_SW1_MAC6,
Codrin Ciubotariu1979db22015-01-12 14:08:30 +0200[diff] [blame]99 SERDES_PRCTL_COUNT /* Keep this item the last one */
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]100};
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]101
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]102enum srds {
103 FSL_SRDS_1 = 0,
104 FSL_SRDS_2 = 1,
105 FSL_SRDS_3 = 2,
106 FSL_SRDS_4 = 3,
107};
108
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]109int is_serdes_configured(enum srds_prtcl device);
Kumar Gala86853d42010-05-22 13:21:39 -0500[diff] [blame]110void fsl_serdes_init(void);
Valentin Longchampf4fe44a2013-10-18 11:47:23 +0200[diff] [blame]111const char *serdes_clock_to_string(u32 clock);
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]112
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]113#ifdef CONFIG_FSL_CORENET
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]114#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
115int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekhac404d612013-07-02 14:42:07 +0530[diff] [blame]116enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]117#else
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]118int serdes_get_first_lane(enum srds_prtcl device);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]119#endif
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]120#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
121void serdes_reset_rx(enum srds_prtcl device);
122#endif
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]123#endif
124
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]125#endif /* __FSL_SERDES_H */