Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 9540368c1683350e064373e5b6d01ef163e1b6ed / . / arch / powerpc / include / asm / fsl_serdes.h
blob: 8e0e190003872928bc3814e028388a9b6e025029 [file] [log] [blame]
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]1/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]5 */
6
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]12enum srds_prtcl {
13 NONE = 0,
14 PCIE1,
15 PCIE2,
16 PCIE3,
17 PCIE4,
18 SATA1,
19 SATA2,
20 SRIO1,
21 SRIO2,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]22 SGMII_FM1_DTSEC1,
23 SGMII_FM1_DTSEC2,
24 SGMII_FM1_DTSEC3,
25 SGMII_FM1_DTSEC4,
26 SGMII_FM1_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]27 SGMII_FM1_DTSEC6,
28 SGMII_FM1_DTSEC9,
29 SGMII_FM1_DTSEC10,
Kumar Gala674e0f42010-07-12 22:51:29 -0500[diff] [blame]30 SGMII_FM2_DTSEC1,
31 SGMII_FM2_DTSEC2,
32 SGMII_FM2_DTSEC3,
33 SGMII_FM2_DTSEC4,
Timur Tabi7920fb12012-08-14 06:47:21 +0000[diff] [blame]34 SGMII_FM2_DTSEC5,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]35 SGMII_FM2_DTSEC6,
36 SGMII_FM2_DTSEC9,
37 SGMII_FM2_DTSEC10,
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]38 SGMII_TSEC1,
39 SGMII_TSEC2,
40 SGMII_TSEC3,
41 SGMII_TSEC4,
42 XAUI_FM1,
43 XAUI_FM2,
44 AURORA,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]45 CPRI1,
46 CPRI2,
47 CPRI3,
48 CPRI4,
49 CPRI5,
50 CPRI6,
51 CPRI7,
52 CPRI8,
53 XAUI_FM1_MAC9,
54 XAUI_FM1_MAC10,
55 XAUI_FM2_MAC9,
56 XAUI_FM2_MAC10,
57 HIGIG_FM1_MAC9,
58 HIGIG_FM1_MAC10,
59 HIGIG_FM2_MAC9,
60 HIGIG_FM2_MAC10,
61 QSGMII_FM1_A, /* A indicates MACs 1-4 */
62 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
63 QSGMII_FM2_A,
64 QSGMII_FM2_B,
Shengzhou Liu4227e492013-11-22 17:39:09 +0800[diff] [blame]65 XFI_FM1_MAC1,
66 XFI_FM1_MAC2,
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]67 XFI_FM1_MAC9,
68 XFI_FM1_MAC10,
69 XFI_FM2_MAC9,
70 XFI_FM2_MAC10,
71 INTERLAKEN,
Prabhakar Kushwaha3e5ce1c2014-01-24 17:51:50 +0530[diff] [blame]72 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
York Sun46571362013-03-25 07:40:06 +0000[diff] [blame]73 QSGMII_SW1_B,
Shengzhou Liu95403682014-10-23 17:20:57 +0800[diff] [blame^]74 SGMII_2500_FM1_DTSEC1,
75 SGMII_2500_FM1_DTSEC2,
76 SGMII_2500_FM1_DTSEC3,
77 SGMII_2500_FM1_DTSEC4,
78 SGMII_2500_FM1_DTSEC5,
79 SGMII_2500_FM1_DTSEC6,
80 SGMII_2500_FM1_DTSEC9,
81 SGMII_2500_FM1_DTSEC10,
82 SGMII_2500_FM2_DTSEC1,
83 SGMII_2500_FM2_DTSEC2,
84 SGMII_2500_FM2_DTSEC3,
85 SGMII_2500_FM2_DTSEC4,
86 SGMII_2500_FM2_DTSEC5,
87 SGMII_2500_FM2_DTSEC6,
88 SGMII_2500_FM2_DTSEC9,
89 SGMII_2500_FM2_DTSEC10,
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]90};
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]91
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]92enum srds {
93 FSL_SRDS_1 = 0,
94 FSL_SRDS_2 = 1,
95 FSL_SRDS_3 = 2,
96 FSL_SRDS_4 = 3,
97};
98
Kumar Galaaf7a9dc2010-04-20 10:20:33 -0500[diff] [blame]99int is_serdes_configured(enum srds_prtcl device);
Kumar Gala86853d42010-05-22 13:21:39 -0500[diff] [blame]100void fsl_serdes_init(void);
Valentin Longchampf4fe44a2013-10-18 11:47:23 +0200[diff] [blame]101const char *serdes_clock_to_string(u32 clock);
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]102
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]103#ifdef CONFIG_FSL_CORENET
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]104#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
105int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
Shaveta Leekhac404d612013-07-02 14:42:07 +0530[diff] [blame]106enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]107#else
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]108int serdes_get_first_lane(enum srds_prtcl device);
York Sun7e0edbd2012-10-08 07:44:15 +0000[diff] [blame]109#endif
Emil Medveb01c81f2010-08-31 22:57:38 -0500[diff] [blame]110#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
111void serdes_reset_rx(enum srds_prtcl device);
112#endif
Emil Medvef6651e62010-08-31 22:57:36 -0500[diff] [blame]113#endif
114
Anton Vorontsov202f9e02008-03-24 17:40:32 +0300[diff] [blame]115#endif /* __FSL_SERDES_H */