blob: ce67b439e8717b876b8242aa40ed10adbd379c9a [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Peng Faneae4de22018-01-10 13:20:37 +08002/*
Gaurav Jain81113a02022-03-24 11:50:27 +05303 * Copyright 2017-2019, 2021 NXP
Peng Faneae4de22018-01-10 13:20:37 +08004 *
5 * Peng Fan <peng.fan@nxp.com>
Peng Faneae4de22018-01-10 13:20:37 +08006 */
7
8#include <common.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07009#include <cpu_func.h>
Simon Glassfc557362022-03-04 08:43:05 -070010#include <event.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060012#include <log.h>
Peng Faneae4de22018-01-10 13:20:37 +080013#include <asm/arch/imx-regs.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Peng Faneae4de22018-01-10 13:20:37 +080015#include <asm/io.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/mach-imx/hab.h>
19#include <asm/mach-imx/boot_mode.h>
20#include <asm/mach-imx/syscounter.h>
Peng Fana35215d2020-07-09 13:39:26 +080021#include <asm/ptrace.h>
Peng Faneae4de22018-01-10 13:20:37 +080022#include <asm/armv8/mmu.h>
Peng Fanc98e0322019-08-27 06:25:58 +000023#include <dm/uclass.h>
Gaurav Jain81113a02022-03-24 11:50:27 +053024#include <dm/device.h>
Peng Fana35215d2020-07-09 13:39:26 +080025#include <efi_loader.h>
Ye Li0513f362019-07-15 01:16:46 -070026#include <env.h>
27#include <env_internal.h>
Peng Faneae4de22018-01-10 13:20:37 +080028#include <errno.h>
29#include <fdt_support.h>
30#include <fsl_wdog.h>
Fedor Rossed2f94a2023-10-16 18:16:14 +020031#include <fuse.h>
Peng Faneae4de22018-01-10 13:20:37 +080032#include <imx_sip.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060033#include <linux/bitops.h>
Fedor Rossed2f94a2023-10-16 18:16:14 +020034#include <linux/bitfield.h>
Peng Faneae4de22018-01-10 13:20:37 +080035
36DECLARE_GLOBAL_DATA_PTR;
37
Stefano Babicf8b509b2019-09-20 08:47:53 +020038#if defined(CONFIG_IMX_HAB)
Peng Faneae4de22018-01-10 13:20:37 +080039struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
40 .bank = 1,
41 .word = 3,
42};
43#endif
44
45int timer_init(void)
46{
47#ifdef CONFIG_SPL_BUILD
48 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
49 unsigned long freq = readl(&sctr->cntfid0);
50
51 /* Update with accurate clock frequency */
52 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
53
54 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
55 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
56#endif
57
58 gd->arch.tbl = 0;
59 gd->arch.tbu = 0;
60
61 return 0;
62}
63
64void enable_tzc380(void)
65{
66 struct iomuxc_gpr_base_regs *gpr =
67 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
68
69 /* Enable TZASC and lock setting */
70 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
71 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010072
73 /*
74 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
75 * order to avoid AXI Bus errors when GPU is in use
76 */
Peng Fanda7a16c2022-04-29 16:18:49 +080077 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010078
79 /*
80 * imx8mn and imx8mp implements the lock bit for
81 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
82 */
Peng Fanda7a16c2022-04-29 16:18:49 +080083 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
Andrey Zhizhikin7c2d23a2022-01-24 21:48:09 +010084
Ye Li4c97c462019-08-27 06:25:34 +000085 /*
86 * set Region 0 attribute to allow secure and non-secure
87 * read/write permission. Found some masters like usb dwc3
88 * controllers can't work with secure memory.
89 */
90 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
Peng Faneae4de22018-01-10 13:20:37 +080091}
92
93void set_wdog_reset(struct wdog_regs *wdog)
94{
95 /*
96 * Output WDOG_B signal to reset external pmic or POR_B decided by
97 * the board design. Without external reset, the peripherals/DDR/
98 * PMIC are not reset, that may cause system working abnormal.
99 * WDZST bit is write-once only bit. Align this bit in kernel,
100 * otherwise kernel code will have no chance to set this bit.
101 */
102 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
103}
104
Marek Vasut003969b2022-12-22 01:46:40 +0100105#ifdef CONFIG_ARMV8_PSCI
106#define PTE_MAP_NS PTE_BLOCK_NS
107#else
108#define PTE_MAP_NS 0
109#endif
110
Peng Faneae4de22018-01-10 13:20:37 +0800111static struct mm_region imx8m_mem_map[] = {
112 {
113 /* ROM */
114 .virt = 0x0UL,
115 .phys = 0x0UL,
116 .size = 0x100000UL,
117 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
118 PTE_BLOCK_OUTER_SHARE
119 }, {
Gary Bisson5c72a452018-11-14 17:55:28 +0100120 /* CAAM */
121 .virt = 0x100000UL,
122 .phys = 0x100000UL,
123 .size = 0x8000UL,
124 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
125 PTE_BLOCK_NON_SHARE |
126 PTE_BLOCK_PXN | PTE_BLOCK_UXN
127 }, {
Marek Vasutb1738e02021-02-25 21:52:26 +0100128 /* OCRAM_S */
129 .virt = 0x180000UL,
130 .phys = 0x180000UL,
131 .size = 0x8000UL,
132 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100133 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Marek Vasutb1738e02021-02-25 21:52:26 +0100134 }, {
Gary Bisson5c72a452018-11-14 17:55:28 +0100135 /* TCM */
136 .virt = 0x7C0000UL,
137 .phys = 0x7C0000UL,
138 .size = 0x80000UL,
139 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE |
Marek Vasut003969b2022-12-22 01:46:40 +0100141 PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
Gary Bisson5c72a452018-11-14 17:55:28 +0100142 }, {
Peng Faneae4de22018-01-10 13:20:37 +0800143 /* OCRAM */
144 .virt = 0x900000UL,
145 .phys = 0x900000UL,
146 .size = 0x200000UL,
147 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100148 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Faneae4de22018-01-10 13:20:37 +0800149 }, {
150 /* AIPS */
151 .virt = 0xB00000UL,
152 .phys = 0xB00000UL,
153 .size = 0x3f500000UL,
154 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
155 PTE_BLOCK_NON_SHARE |
156 PTE_BLOCK_PXN | PTE_BLOCK_UXN
157 }, {
158 /* DRAM1 */
159 .virt = 0x40000000UL,
160 .phys = 0x40000000UL,
Peng Fanb749b5e2019-08-27 06:25:27 +0000161 .size = PHYS_SDRAM_SIZE,
Peng Faneae4de22018-01-10 13:20:37 +0800162 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100163 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Fanb749b5e2019-08-27 06:25:27 +0000164#ifdef PHYS_SDRAM_2_SIZE
Peng Faneae4de22018-01-10 13:20:37 +0800165 }, {
166 /* DRAM2 */
167 .virt = 0x100000000UL,
168 .phys = 0x100000000UL,
Peng Fanb749b5e2019-08-27 06:25:27 +0000169 .size = PHYS_SDRAM_2_SIZE,
Peng Faneae4de22018-01-10 13:20:37 +0800170 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
Marek Vasut003969b2022-12-22 01:46:40 +0100171 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
Peng Fanb749b5e2019-08-27 06:25:27 +0000172#endif
Peng Faneae4de22018-01-10 13:20:37 +0800173 }, {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800174 /* empty entrie to split table entry 5 if needed when TEEs are used */
175 0,
176 }, {
Peng Faneae4de22018-01-10 13:20:37 +0800177 /* List terminator */
178 0,
179 }
180};
181
182struct mm_region *mem_map = imx8m_mem_map;
183
Marek Vasute48aac02021-02-27 14:59:00 +0100184static unsigned int imx8m_find_dram_entry_in_mem_map(void)
185{
186 int i;
187
188 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
Tom Rinibb4dd962022-11-16 13:10:37 -0500189 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
Marek Vasute48aac02021-02-27 14:59:00 +0100190 return i;
191
192 hang(); /* Entry not found, this must never happen. */
193}
194
Peng Fanb749b5e2019-08-27 06:25:27 +0000195void enable_caches(void)
196{
Ye Li453bfcb2022-04-07 15:55:56 +0800197 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
198 * If OPTEE does not run, still update the MMU table according to dram banks structure
199 * to set correct dram size from board_phys_sdram_size
200 */
201 int i = 0;
202 /*
203 * please make sure that entry initial value matches
204 * imx8m_mem_map for DRAM1
205 */
206 int entry = imx8m_find_dram_entry_in_mem_map();
207 u64 attrs = imx8m_mem_map[entry].attrs;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800208
Ye Li453bfcb2022-04-07 15:55:56 +0800209 while (i < CONFIG_NR_DRAM_BANKS &&
210 entry < ARRAY_SIZE(imx8m_mem_map)) {
211 if (gd->bd->bi_dram[i].start == 0)
212 break;
213 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
214 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
215 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
216 imx8m_mem_map[entry].attrs = attrs;
217 debug("Added memory mapping (%d): %llx %llx\n", entry,
218 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
219 i++; entry++;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800220 }
Peng Fanb749b5e2019-08-27 06:25:27 +0000221
222 icache_enable();
223 dcache_enable();
224}
225
Peng Fanfa35c3d2020-07-09 15:26:06 +0800226__weak int board_phys_sdram_size(phys_size_t *size)
227{
228 if (!size)
229 return -EINVAL;
230
231 *size = PHYS_SDRAM_SIZE;
Ye Li453bfcb2022-04-07 15:55:56 +0800232
233#ifdef PHYS_SDRAM_2_SIZE
234 *size += PHYS_SDRAM_2_SIZE;
235#endif
Peng Fanfa35c3d2020-07-09 15:26:06 +0800236 return 0;
237}
238
239int dram_init(void)
240{
241 phys_size_t sdram_size;
242 int ret;
243
244 ret = board_phys_sdram_size(&sdram_size);
245 if (ret)
246 return ret;
247
248 /* rom_pointer[1] contains the size of TEE occupies */
Elena Popa65c9edb2023-08-08 14:58:26 +0300249 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
Peng Fanfa35c3d2020-07-09 15:26:06 +0800250 gd->ram_size = sdram_size - rom_pointer[1];
251 else
252 gd->ram_size = sdram_size;
253
Peng Fanfa35c3d2020-07-09 15:26:06 +0800254 return 0;
255}
256
257int dram_init_banksize(void)
258{
259 int bank = 0;
260 int ret;
261 phys_size_t sdram_size;
Ye Li453bfcb2022-04-07 15:55:56 +0800262 phys_size_t sdram_b1_size, sdram_b2_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800263
264 ret = board_phys_sdram_size(&sdram_size);
265 if (ret)
266 return ret;
267
Ye Li453bfcb2022-04-07 15:55:56 +0800268 /* Bank 1 can't cross over 4GB space */
269 if (sdram_size > 0xc0000000) {
270 sdram_b1_size = 0xc0000000;
271 sdram_b2_size = sdram_size - 0xc0000000;
272 } else {
273 sdram_b1_size = sdram_size;
274 sdram_b2_size = 0;
275 }
276
Peng Fanfa35c3d2020-07-09 15:26:06 +0800277 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
Elena Popa65c9edb2023-08-08 14:58:26 +0300278 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800279 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
280 phys_size_t optee_size = (size_t)rom_pointer[1];
281
282 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
Ye Li453bfcb2022-04-07 15:55:56 +0800283 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
Peng Fanfa35c3d2020-07-09 15:26:06 +0800284 if (++bank >= CONFIG_NR_DRAM_BANKS) {
285 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
286 return -1;
287 }
288
289 gd->bd->bi_dram[bank].start = optee_start + optee_size;
290 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
Ye Li453bfcb2022-04-07 15:55:56 +0800291 sdram_b1_size - gd->bd->bi_dram[bank].start;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800292 }
293 } else {
Ye Li453bfcb2022-04-07 15:55:56 +0800294 gd->bd->bi_dram[bank].size = sdram_b1_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800295 }
296
Ye Li453bfcb2022-04-07 15:55:56 +0800297 if (sdram_b2_size) {
298 if (++bank >= CONFIG_NR_DRAM_BANKS) {
299 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
300 return -1;
301 }
302 gd->bd->bi_dram[bank].start = 0x100000000UL;
303 gd->bd->bi_dram[bank].size = sdram_b2_size;
Peng Fanfa35c3d2020-07-09 15:26:06 +0800304 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800305
306 return 0;
307}
308
309phys_size_t get_effective_memsize(void)
310{
Ye Li453bfcb2022-04-07 15:55:56 +0800311 int ret;
312 phys_size_t sdram_size;
313 phys_size_t sdram_b1_size;
314 ret = board_phys_sdram_size(&sdram_size);
315 if (!ret) {
316 /* Bank 1 can't cross over 4GB space */
317 if (sdram_size > 0xc0000000) {
318 sdram_b1_size = 0xc0000000;
319 } else {
320 sdram_b1_size = sdram_size;
321 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800322
Elena Popa65c9edb2023-08-08 14:58:26 +0300323 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
324 rom_pointer[1]) {
Ye Li453bfcb2022-04-07 15:55:56 +0800325 /* We will relocate u-boot to Top of dram1. Tee position has two cases:
326 * 1. At the top of dram1, Then return the size removed optee size.
327 * 2. In the middle of dram1, return the size of dram1.
328 */
329 if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
330 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
331 }
332
333 return sdram_b1_size;
334 } else {
335 return PHYS_SDRAM_SIZE;
336 }
Peng Fanfa35c3d2020-07-09 15:26:06 +0800337}
338
Heinrich Schuchardt51a9aac2023-08-12 20:16:58 +0200339phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
Frieder Schrempf159879e2021-06-07 14:36:44 +0200340{
Marek Vasutdcbbf782022-04-14 15:51:46 +0200341 ulong top_addr;
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800342
Frieder Schrempf159879e2021-06-07 14:36:44 +0200343 /*
344 * Some IPs have their accessible address space restricted by
345 * the interconnect. Let's make sure U-Boot only ever uses the
346 * space below the 4G address boundary (which is 3GiB big),
347 * even when the effective available memory is bigger.
348 */
Marek Vasutdcbbf782022-04-14 15:51:46 +0200349 top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800350
351 /*
352 * rom_pointer[0] stores the TEE memory start address.
353 * rom_pointer[1] stores the size TEE uses.
354 * We need to reserve the memory region for TEE.
355 */
Marek Vasut9ca966e2022-12-22 01:46:38 +0100356 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
357 rom_pointer[1] && top_addr > rom_pointer[0])
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800358 top_addr = rom_pointer[0];
Frieder Schrempf159879e2021-06-07 14:36:44 +0200359
Ying-Chun Liu (PaulLiu)ed55caf2021-08-23 10:43:06 +0800360 return top_addr;
Frieder Schrempf159879e2021-06-07 14:36:44 +0200361}
362
Peng Fan1caffdf2019-08-27 06:25:17 +0000363static u32 get_cpu_variant_type(u32 type)
364{
365 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
366 struct fuse_bank *bank = &ocotp->bank[1];
367 struct fuse_bank1_regs *fuse =
368 (struct fuse_bank1_regs *)bank->fuse_regs;
369
370 u32 value = readl(&fuse->tester4);
371
Peng Fan67815082020-02-05 17:34:54 +0800372 if (type == MXC_CPU_IMX8MQ) {
373 if ((value & 0x3) == 0x2)
374 return MXC_CPU_IMX8MD;
375 else if (value & 0x200000)
376 return MXC_CPU_IMX8MQL;
377
378 } else if (type == MXC_CPU_IMX8MM) {
Peng Fan1caffdf2019-08-27 06:25:17 +0000379 switch (value & 0x3) {
380 case 2:
381 if (value & 0x1c0000)
382 return MXC_CPU_IMX8MMDL;
383 else
384 return MXC_CPU_IMX8MMD;
385 case 3:
386 if (value & 0x1c0000)
387 return MXC_CPU_IMX8MMSL;
388 else
389 return MXC_CPU_IMX8MMS;
390 default:
391 if (value & 0x1c0000)
392 return MXC_CPU_IMX8MML;
393 break;
394 }
Peng Fan1a07d912020-02-05 17:39:27 +0800395 } else if (type == MXC_CPU_IMX8MN) {
396 switch (value & 0x3) {
397 case 2:
Ye Li715180e2021-03-19 15:57:11 +0800398 if (value & 0x1000000) {
399 if (value & 0x10000000) /* MIPI DSI */
400 return MXC_CPU_IMX8MNUD;
401 else
402 return MXC_CPU_IMX8MNDL;
403 } else {
Peng Fan1a07d912020-02-05 17:39:27 +0800404 return MXC_CPU_IMX8MND;
Ye Li715180e2021-03-19 15:57:11 +0800405 }
Peng Fan1a07d912020-02-05 17:39:27 +0800406 case 3:
Ye Li715180e2021-03-19 15:57:11 +0800407 if (value & 0x1000000) {
408 if (value & 0x10000000) /* MIPI DSI */
409 return MXC_CPU_IMX8MNUS;
410 else
411 return MXC_CPU_IMX8MNSL;
412 } else {
Peng Fan1a07d912020-02-05 17:39:27 +0800413 return MXC_CPU_IMX8MNS;
Ye Li715180e2021-03-19 15:57:11 +0800414 }
Peng Fan1a07d912020-02-05 17:39:27 +0800415 default:
Ye Li715180e2021-03-19 15:57:11 +0800416 if (value & 0x1000000) {
417 if (value & 0x10000000) /* MIPI DSI */
418 return MXC_CPU_IMX8MNUQ;
419 else
420 return MXC_CPU_IMX8MNL;
421 }
Peng Fan1a07d912020-02-05 17:39:27 +0800422 break;
423 }
Ye Lid2d754f2020-04-20 20:12:54 -0700424 } else if (type == MXC_CPU_IMX8MP) {
425 u32 value0 = readl(&fuse->tester3);
426 u32 flag = 0;
427
428 if ((value0 & 0xc0000) == 0x80000)
429 return MXC_CPU_IMX8MPD;
430
431 /* vpu disabled */
432 if ((value0 & 0x43000000) == 0x43000000)
433 flag = 1;
434
435 /* npu disabled*/
436 if ((value & 0x8) == 0x8)
Peng Fan0386e7f2022-04-07 15:55:52 +0800437 flag |= BIT(1);
Ye Lid2d754f2020-04-20 20:12:54 -0700438
439 /* isp disabled */
440 if ((value & 0x3) == 0x3)
Peng Fan0386e7f2022-04-07 15:55:52 +0800441 flag |= BIT(2);
442
443 /* gpu disabled */
444 if ((value & 0xc0) == 0xc0)
445 flag |= BIT(3);
446
447 /* lvds disabled */
448 if ((value & 0x180000) == 0x180000)
449 flag |= BIT(4);
450
451 /* mipi dsi disabled */
452 if ((value & 0x60000) == 0x60000)
453 flag |= BIT(5);
Ye Lid2d754f2020-04-20 20:12:54 -0700454
455 switch (flag) {
Peng Fan0386e7f2022-04-07 15:55:52 +0800456 case 0x3f:
457 return MXC_CPU_IMX8MPUL;
Ye Lid2d754f2020-04-20 20:12:54 -0700458 case 7:
459 return MXC_CPU_IMX8MPL;
Ye Lid2d754f2020-04-20 20:12:54 -0700460 case 2:
461 return MXC_CPU_IMX8MP6;
Ye Lid2d754f2020-04-20 20:12:54 -0700462 default:
463 break;
464 }
465
Peng Fan1caffdf2019-08-27 06:25:17 +0000466 }
467
468 return type;
469}
470
Peng Faneae4de22018-01-10 13:20:37 +0800471u32 get_cpu_rev(void)
472{
473 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
474 u32 reg = readl(&ana_pll->digprog);
475 u32 type = (reg >> 16) & 0xff;
Peng Fan1caffdf2019-08-27 06:25:17 +0000476 u32 major_low = (reg >> 8) & 0xff;
Peng Faneae4de22018-01-10 13:20:37 +0800477 u32 rom_version;
478
479 reg &= 0xff;
480
Peng Fan69cec072019-12-27 10:14:02 +0800481 /* iMX8MP */
482 if (major_low == 0x43) {
Ye Lid2d754f2020-04-20 20:12:54 -0700483 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
Peng Fan69cec072019-12-27 10:14:02 +0800484 } else if (major_low == 0x42) {
485 /* iMX8MN */
Peng Fan1a07d912020-02-05 17:39:27 +0800486 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
Peng Fan5d2f2062019-06-27 17:23:49 +0800487 } else if (major_low == 0x41) {
Peng Fan1caffdf2019-08-27 06:25:17 +0000488 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
489 } else {
490 if (reg == CHIP_REV_1_0) {
491 /*
Peng Fanc23fbdd2019-10-16 10:24:17 +0000492 * For B0 chip, the DIGPROG is not updated,
493 * it is still TO1.0. we have to check ROM
494 * version or OCOTP_READ_FUSE_DATA.
495 * 0xff0055aa is magic number for B1.
Peng Fan1caffdf2019-08-27 06:25:17 +0000496 */
Peng Fanc23fbdd2019-10-16 10:24:17 +0000497 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
Ye Lic963ed12021-03-19 15:57:16 +0800498 /*
499 * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
500 * so have to check ROM to distinguish them
501 */
502 rom_version = readl((void __iomem *)ROM_VERSION_B0);
503 rom_version &= 0xff;
504 if (rom_version == CHIP_REV_2_2)
505 reg = CHIP_REV_2_2;
506 else
507 reg = CHIP_REV_2_1;
Peng Fanc23fbdd2019-10-16 10:24:17 +0000508 } else {
509 rom_version =
510 readl((void __iomem *)ROM_VERSION_A0);
511 if (rom_version != CHIP_REV_1_0) {
512 rom_version = readl((void __iomem *)ROM_VERSION_B0);
Patrick Wildtd4a78b92019-11-19 09:42:06 +0100513 rom_version &= 0xff;
Peng Fanc23fbdd2019-10-16 10:24:17 +0000514 if (rom_version == CHIP_REV_2_0)
515 reg = CHIP_REV_2_0;
516 }
Peng Fan1caffdf2019-08-27 06:25:17 +0000517 }
Peng Faneae4de22018-01-10 13:20:37 +0800518 }
Peng Fan67815082020-02-05 17:34:54 +0800519
520 type = get_cpu_variant_type(type);
Peng Faneae4de22018-01-10 13:20:37 +0800521 }
522
523 return (type << 12) | reg;
524}
525
526static void imx_set_wdog_powerdown(bool enable)
527{
528 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
529 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
530 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
531
532 /* Write to the PDE (Power Down Enable) bit */
533 writew(enable, &wdog1->wmcr);
534 writew(enable, &wdog2->wmcr);
535 writew(enable, &wdog3->wmcr);
536}
537
Simon Glassb8357c12023-08-21 21:16:56 -0600538static int imx8m_check_clock(void)
Peng Fanc98e0322019-08-27 06:25:58 +0000539{
540 struct udevice *dev;
541 int ret;
542
Peng Fan3c073342019-10-16 03:01:51 +0000543 if (CONFIG_IS_ENABLED(CLK)) {
544 ret = uclass_get_device_by_name(UCLASS_CLK,
545 "clock-controller@30380000",
546 &dev);
547 if (ret < 0) {
548 printf("Failed to find clock node. Check device tree\n");
549 return ret;
550 }
Peng Fanc98e0322019-08-27 06:25:58 +0000551 }
552
553 return 0;
554}
Simon Glassb8357c12023-08-21 21:16:56 -0600555EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8m_check_clock);
Peng Fanc98e0322019-08-27 06:25:58 +0000556
Marek Vasutf7b184e2022-09-19 21:37:07 +0200557static void imx8m_setup_snvs(void)
558{
559 /* Enable SNVS clock */
560 clock_enable(CCGR_SNVS, 1);
561 /* Initialize glitch detect */
562 writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
563 /* Clear interrupt status */
564 writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
565}
566
Marek Vasut829858a2022-12-22 01:46:42 +0100567static void imx8m_setup_csu_tzasc(void)
568{
569 const uintptr_t tzasc_base[4] = {
570 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
571 };
572 int i, j;
573
574 if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
575 return;
576
577 /* CSU */
578 for (i = 0; i < 64; i++)
579 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
580
581 /* TZASC */
582 for (j = 0; j < 4; j++) {
583 writel(0x77777777, (void *)(tzasc_base[j]));
584 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
585 for (i = 0; i <= 0x10; i += 4)
586 writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
587 }
588}
589
Peng Faneae4de22018-01-10 13:20:37 +0800590int arch_cpu_init(void)
591{
Peng Fanc0b30d72019-04-17 09:41:16 +0000592 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
Marek Vasut3ea500a2022-04-13 00:41:52 +0200593
594#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
595 icache_enable();
596#endif
597
Peng Faneae4de22018-01-10 13:20:37 +0800598 /*
Peng Fand0ca2892019-08-27 06:25:37 +0000599 * ROM might disable clock for SCTR,
600 * enable the clock before timer_init.
601 */
602 if (IS_ENABLED(CONFIG_SPL_BUILD))
603 clock_enable(CCGR_SCTR, 1);
604 /*
Peng Faneae4de22018-01-10 13:20:37 +0800605 * Init timer at very early state, because sscg pll setting
606 * will use it
607 */
608 timer_init();
609
610 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
611 clock_init();
612 imx_set_wdog_powerdown(false);
Peng Fan9cf2aa32020-07-09 13:52:41 +0800613
614 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
615 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
Ye Li715180e2021-03-19 15:57:11 +0800616 is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
Peng Fan9cf2aa32020-07-09 13:52:41 +0800617 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
618 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
619 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
620 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
621 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
622
623 writel(0x1, &pgc_core2->pgcr);
624 writel(0x1, &pgc_core3->pgcr);
Ye Li715180e2021-03-19 15:57:11 +0800625 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
Peng Fan9cf2aa32020-07-09 13:52:41 +0800626 writel(0x1, &pgc_core1->pgcr);
627 writel(0xE, &gpc->cpu_pgc_dn_trg);
628 } else {
629 writel(0xC, &gpc->cpu_pgc_dn_trg);
630 }
631 }
Peng Faneae4de22018-01-10 13:20:37 +0800632 }
633
Peng Fanc0b30d72019-04-17 09:41:16 +0000634 if (is_imx8mq()) {
635 clock_enable(CCGR_OCOTP, 1);
636 if (readl(&ocotp->ctrl) & 0x200)
637 writel(0x200, &ocotp->ctrl_clr);
638 }
639
Marek Vasutf7b184e2022-09-19 21:37:07 +0200640 imx8m_setup_snvs();
641
Marek Vasut829858a2022-12-22 01:46:42 +0100642 imx8m_setup_csu_tzasc();
643
Peng Faneae4de22018-01-10 13:20:37 +0800644 return 0;
645}
646
Peng Fanc9823b02019-09-16 03:09:36 +0000647#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
648struct rom_api *g_rom_api = (struct rom_api *)0x980;
Peng Fanc9823b02019-09-16 03:09:36 +0000649#endif
650
Marek Vasut520ded02021-07-03 04:55:33 +0200651#if defined(CONFIG_IMX8M)
652#include <spl.h>
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200653int imx8m_detect_secondary_image_boot(void)
Marek Vasut520ded02021-07-03 04:55:33 +0200654{
655 u32 *rom_log_addr = (u32 *)0x9e0;
656 u32 *rom_log;
657 u8 event_id;
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200658 int i, boot_secondary = 0;
Marek Vasut520ded02021-07-03 04:55:33 +0200659
660 /* If the ROM event log pointer is not valid. */
661 if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
662 *rom_log_addr & 0x3)
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200663 return -EINVAL;
Marek Vasut520ded02021-07-03 04:55:33 +0200664
665 /* Parse the ROM event ID version 2 log */
666 rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
667 for (i = 0; i < 128; i++) {
668 event_id = rom_log[i] >> 24;
669 switch (event_id) {
670 case 0x00: /* End of list */
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200671 return boot_secondary;
Marek Vasut520ded02021-07-03 04:55:33 +0200672 /* Log entries with 1 parameter, skip 1 */
673 case 0x80: /* Start to perform the device initialization */
674 case 0x81: /* The boot device initialization completes */
Fedor Ross7e02ff62022-04-14 18:36:23 +0200675 case 0x82: /* Starts to execute boot device driver pre-config */
Marek Vasut520ded02021-07-03 04:55:33 +0200676 case 0x8f: /* The boot device initialization fails */
677 case 0x90: /* Start to read data from boot device */
678 case 0x91: /* Reading data from boot device completes */
679 case 0x9f: /* Reading data from boot device fails */
680 i += 1;
681 continue;
682 /* Log entries with 2 parameters, skip 2 */
683 case 0xa0: /* Image authentication result */
684 case 0xc0: /* Jump to the boot image soon */
685 i += 2;
686 continue;
687 /* Boot from the secondary boot image */
688 case 0x51:
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200689 boot_secondary = 1;
Marek Vasut520ded02021-07-03 04:55:33 +0200690 continue;
691 default:
692 continue;
693 }
694 }
695
Fedor Ross5bc5f0e2023-10-16 18:16:13 +0200696 return boot_secondary;
697}
698
699int spl_mmc_emmc_boot_partition(struct mmc *mmc)
700{
701 int part, ret;
702
703 part = default_spl_mmc_emmc_boot_partition(mmc);
704 if (part == 0)
705 return part;
706
707 ret = imx8m_detect_secondary_image_boot();
708 if (ret < 0) {
709 printf("Could not get boot partition! Using %d\n", part);
710 return part;
711 }
712
713 if (ret == 1) {
714 /*
715 * Swap the eMMC boot partitions in case there was a
716 * fallback event (i.e. primary image was corrupted
717 * and that corruption was recognized by the BootROM),
718 * so the SPL loads the rest of the U-Boot from the
719 * correct eMMC boot partition, since the BootROM
720 * leaves the boot partition set to the corrupted one.
721 */
722 if (part == 1)
723 part = 2;
724 else if (part == 2)
725 part = 1;
726 }
727
Marek Vasut520ded02021-07-03 04:55:33 +0200728 return part;
729}
730#endif
731
Fedor Rossed2f94a2023-10-16 18:16:14 +0200732#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
733#define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
734unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
735 unsigned long raw_sect)
736{
737 u32 val, offset;
738
739 if (fuse_read(2, 1, &val)) {
740 debug("Error reading fuse!\n");
741 return raw_sect;
742 }
743
744 val = FIELD_GET(IMG_CNTN_SET1_OFFSET, val);
745 if (val > 10) {
746 debug("Secondary image boot disabled!\n");
747 return raw_sect;
748 }
749
750 if (val == 0)
751 offset = SZ_4M;
752 else if (val == 1)
753 offset = SZ_2M;
754 else if (val == 2)
755 offset = SZ_1M;
756 else /* flash.bin offset = 1 MiB * 2^n */
757 offset = SZ_1M << val;
758
759 offset /= 512;
760 offset -= CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET;
761
762 if (imx8m_detect_secondary_image_boot())
763 raw_sect += offset;
764
765 return raw_sect;
766}
767#endif
768
Peng Faneae4de22018-01-10 13:20:37 +0800769bool is_usb_boot(void)
770{
771 return get_boot_device() == USB_BOOT;
772}
773
774#ifdef CONFIG_OF_SYSTEM_SETUP
Peng Fan435dc122020-07-09 14:06:49 +0800775bool check_fdt_new_path(void *blob)
776{
777 const char *soc_path = "/soc@0";
778 int nodeoff;
779
780 nodeoff = fdt_path_offset(blob, soc_path);
781 if (nodeoff < 0)
782 return false;
783
784 return true;
785}
786
787static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
788{
789 int i = 0;
790 int rc;
791 int nodeoff;
792 const char *status = "disabled";
793
794 for (i = 0; i < size_array; i++) {
795 nodeoff = fdt_path_offset(blob, nodes_path[i]);
796 if (nodeoff < 0)
797 continue; /* Not found, skip it */
798
Rasmus Villemoes8ab149a2023-05-22 11:27:28 +0200799 debug("Found %s node\n", nodes_path[i]);
Peng Fan435dc122020-07-09 14:06:49 +0800800
801add_status:
802 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
803 if (rc) {
804 if (rc == -FDT_ERR_NOSPACE) {
805 rc = fdt_increase_size(blob, 512);
806 if (!rc)
807 goto add_status;
808 }
809 printf("Unable to update property %s:%s, err=%s\n",
810 nodes_path[i], "status", fdt_strerror(rc));
811 } else {
812 printf("Modify %s:%s disabled\n",
813 nodes_path[i], "status");
814 }
815 }
816
817 return 0;
818}
819
820#ifdef CONFIG_IMX8MQ
821bool check_dcss_fused(void)
822{
823 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
824 struct fuse_bank *bank = &ocotp->bank[1];
825 struct fuse_bank1_regs *fuse =
826 (struct fuse_bank1_regs *)bank->fuse_regs;
827 u32 value = readl(&fuse->tester4);
828
829 if (value & 0x4000000)
830 return true;
831
832 return false;
833}
834
835static int disable_mipi_dsi_nodes(void *blob)
836{
837 static const char * const nodes_path[] = {
838 "/mipi_dsi@30A00000",
839 "/mipi_dsi_bridge@30A00000",
840 "/dsi_phy@30A00300",
841 "/soc@0/bus@30800000/mipi_dsi@30a00000",
Peng Fan7d4195c2021-03-19 15:57:13 +0800842 "/soc@0/bus@30800000/dphy@30a00300",
843 "/soc@0/bus@30800000/mipi-dsi@30a00000",
Peng Fan435dc122020-07-09 14:06:49 +0800844 };
845
846 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
847}
848
849static int disable_dcss_nodes(void *blob)
850{
851 static const char * const nodes_path[] = {
852 "/dcss@0x32e00000",
853 "/dcss@32e00000",
854 "/hdmi@32c00000",
855 "/hdmi_cec@32c33800",
856 "/hdmi_drm@32c00000",
857 "/display-subsystem",
858 "/sound-hdmi",
859 "/sound-hdmi-arc",
860 "/soc@0/bus@32c00000/display-controller@32e00000",
861 "/soc@0/bus@32c00000/hdmi@32c00000",
862 };
863
864 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
865}
866
867static int check_mipi_dsi_nodes(void *blob)
868{
869 static const char * const lcdif_path[] = {
870 "/lcdif@30320000",
Peng Fan7d4195c2021-03-19 15:57:13 +0800871 "/soc@0/bus@30000000/lcdif@30320000",
872 "/soc@0/bus@30000000/lcd-controller@30320000"
Peng Fan435dc122020-07-09 14:06:49 +0800873 };
874 static const char * const mipi_dsi_path[] = {
875 "/mipi_dsi@30A00000",
876 "/soc@0/bus@30800000/mipi_dsi@30a00000"
877 };
878 static const char * const lcdif_ep_path[] = {
879 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
Peng Fan7d4195c2021-03-19 15:57:13 +0800880 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
881 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
Peng Fan435dc122020-07-09 14:06:49 +0800882 };
883 static const char * const mipi_dsi_ep_path[] = {
884 "/mipi_dsi@30A00000/port@1/endpoint",
Peng Fan7d4195c2021-03-19 15:57:13 +0800885 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
886 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
Peng Fan435dc122020-07-09 14:06:49 +0800887 };
888
889 int lookup_node;
890 int nodeoff;
891 bool new_path = check_fdt_new_path(blob);
892 int i = new_path ? 1 : 0;
893
894 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
895 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
896 /*
897 * If can't find lcdif node or lcdif node is disabled,
898 * then disable all mipi dsi, since they only can input
899 * from DCSS
900 */
901 return disable_mipi_dsi_nodes(blob);
902 }
903
904 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
905 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
906 return 0;
907
908 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
909 if (nodeoff < 0) {
910 /*
911 * If can't find lcdif endpoint, then disable all mipi dsi,
912 * since they only can input from DCSS
913 */
914 return disable_mipi_dsi_nodes(blob);
915 }
916
917 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
918 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
919
920 if (nodeoff > 0 && nodeoff == lookup_node)
921 return 0;
922
923 return disable_mipi_dsi_nodes(blob);
924}
925#endif
926
927int disable_vpu_nodes(void *blob)
928{
929 static const char * const nodes_path_8mq[] = {
930 "/vpu@38300000",
931 "/soc@0/vpu@38300000"
932 };
933
934 static const char * const nodes_path_8mm[] = {
935 "/vpu_g1@38300000",
936 "/vpu_g2@38310000",
937 "/vpu_h1@38320000"
938 };
939
940 static const char * const nodes_path_8mp[] = {
941 "/vpu_g1@38300000",
942 "/vpu_g2@38310000",
943 "/vpu_vc8000e@38320000"
944 };
945
946 if (is_imx8mq())
947 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
948 else if (is_imx8mm())
949 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
950 else if (is_imx8mp())
951 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
952 else
953 return -EPERM;
954}
955
Ye Liee337ce2021-03-19 15:57:09 +0800956#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
957static int low_drive_gpu_freq(void *blob)
958{
959 static const char *nodes_path_8mn[] = {
960 "/gpu@38000000",
961 "/soc@0/gpu@38000000"
962 };
963
964 int nodeoff, cnt, i;
965 u32 assignedclks[7];
966
967 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
968 if (nodeoff < 0)
969 return nodeoff;
970
971 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
972 if (cnt < 0)
973 return cnt;
974
975 if (cnt != 7)
976 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
Heinrich Schuchardt72c891f2023-04-18 01:37:21 +0200977 if (cnt < 2)
978 return -1;
Ye Liee337ce2021-03-19 15:57:09 +0800979
980 assignedclks[cnt - 1] = 200000000;
981 assignedclks[cnt - 2] = 200000000;
982
983 for (i = 0; i < cnt; i++) {
984 debug("<%u>, ", assignedclks[i]);
985 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
986 }
987 debug("\n");
988
989 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
990}
991#endif
992
Peng Fanf5f9b8e2022-04-07 15:55:53 +0800993static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
994{
995 int lookup_node;
996 int nodeoff;
997
998 nodeoff = fdt_path_offset(blob, ep1);
999 if (nodeoff) {
1000 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
1001 nodeoff = fdt_path_offset(blob, ep2);
1002
1003 if (nodeoff > 0 && nodeoff == lookup_node)
1004 return true;
1005 }
1006
1007 return false;
1008}
1009
1010int disable_dsi_lcdif_nodes(void *blob)
1011{
1012 int ret;
1013
1014 static const char * const dsi_path_8mp[] = {
1015 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
1016 };
1017
1018 static const char * const lcdif_path_8mp[] = {
1019 "/soc@0/bus@32c00000/lcd-controller@32e80000"
1020 };
1021
1022 static const char * const lcdif_ep_path_8mp[] = {
1023 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
1024 };
1025 static const char * const dsi_ep_path_8mp[] = {
1026 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
1027 };
1028
1029 ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
1030 if (ret)
1031 return ret;
1032
1033 if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
1034 /* Disable lcdif node */
1035 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1036 }
1037
1038 return 0;
1039}
1040
1041int disable_lvds_lcdif_nodes(void *blob)
1042{
1043 int ret, i;
1044
1045 static const char * const ldb_path_8mp[] = {
1046 "/soc@0/bus@32c00000/ldb@32ec005c",
1047 "/soc@0/bus@32c00000/phy@32ec0128"
1048 };
1049
1050 static const char * const lcdif_path_8mp[] = {
1051 "/soc@0/bus@32c00000/lcd-controller@32e90000"
1052 };
1053
1054 static const char * const lcdif_ep_path_8mp[] = {
1055 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
1056 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
1057 };
1058 static const char * const ldb_ep_path_8mp[] = {
1059 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1060 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1061 };
1062
1063 ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1064 if (ret)
1065 return ret;
1066
1067 for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1068 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1069 /* Disable lcdif node */
1070 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1071 }
1072 }
1073
1074 return 0;
1075}
1076
Peng Fan435dc122020-07-09 14:06:49 +08001077int disable_gpu_nodes(void *blob)
1078{
1079 static const char * const nodes_path_8mn[] = {
Peng Fan7d4195c2021-03-19 15:57:13 +08001080 "/gpu@38000000",
1081 "/soc@/gpu@38000000"
Peng Fan435dc122020-07-09 14:06:49 +08001082 };
1083
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001084 static const char * const nodes_path_8mp[] = {
1085 "/gpu3d@38000000",
1086 "/gpu2d@38008000"
1087 };
1088
1089 if (is_imx8mp())
1090 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1091 else
1092 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
Peng Fan435dc122020-07-09 14:06:49 +08001093}
1094
1095int disable_npu_nodes(void *blob)
1096{
1097 static const char * const nodes_path_8mp[] = {
1098 "/vipsi@38500000"
1099 };
1100
1101 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1102}
1103
1104int disable_isp_nodes(void *blob)
1105{
1106 static const char * const nodes_path_8mp[] = {
1107 "/soc@0/bus@32c00000/camera/isp@32e10000",
1108 "/soc@0/bus@32c00000/camera/isp@32e20000"
1109 };
1110
1111 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1112}
1113
1114int disable_dsp_nodes(void *blob)
1115{
1116 static const char * const nodes_path_8mp[] = {
1117 "/dsp@3b6e8000"
1118 };
1119
1120 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1121}
1122
Ye Li26517af2021-03-19 15:57:12 +08001123static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1124{
1125 static const char * const thermal_path[] = {
1126 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1127 };
1128
1129 int nodeoff, cnt, i, ret, j;
1130 u32 cooling_dev[12];
1131
1132 for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1133 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1134 if (nodeoff < 0)
1135 continue; /* Not found, skip it */
1136
1137 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1138 if (cnt < 0)
1139 continue;
1140
1141 if (cnt != 12)
1142 printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1143
1144 for (j = 0; j < cnt; j++)
1145 cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1146
1147 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1148 sizeof(u32) * (12 - disabled_cores * 3));
1149 if (ret < 0) {
1150 printf("Warning: %s, cooling-device setprop failed %d\n",
1151 thermal_path[i], ret);
1152 continue;
1153 }
1154
1155 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1156 }
1157}
1158
1159static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1160{
1161 static const char * const pmu_path[] = {
1162 "/pmu"
1163 };
1164
1165 int nodeoff, cnt, i, ret, j;
1166 u32 irq_affinity[4];
1167
1168 for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1169 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1170 if (nodeoff < 0)
1171 continue; /* Not found, skip it */
1172
1173 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1174 irq_affinity, 4);
1175 if (cnt < 0)
1176 continue;
1177
1178 if (cnt != 4)
1179 printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1180
1181 for (j = 0; j < cnt; j++)
1182 irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1183
1184 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1185 sizeof(u32) * (4 - disabled_cores));
1186 if (ret < 0) {
1187 printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1188 pmu_path[i], ret);
1189 continue;
1190 }
1191
1192 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1193 }
1194}
1195
Peng Fan435dc122020-07-09 14:06:49 +08001196static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1197{
1198 static const char * const nodes_path[] = {
1199 "/cpus/cpu@1",
1200 "/cpus/cpu@2",
1201 "/cpus/cpu@3",
1202 };
1203 u32 i = 0;
1204 int rc;
1205 int nodeoff;
1206
1207 if (disabled_cores > 3)
1208 return -EINVAL;
1209
1210 i = 3 - disabled_cores;
1211
1212 for (; i < 3; i++) {
1213 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1214 if (nodeoff < 0)
1215 continue; /* Not found, skip it */
1216
1217 debug("Found %s node\n", nodes_path[i]);
1218
1219 rc = fdt_del_node(blob, nodeoff);
1220 if (rc < 0) {
1221 printf("Unable to delete node %s, err=%s\n",
1222 nodes_path[i], fdt_strerror(rc));
1223 } else {
1224 printf("Delete node %s\n", nodes_path[i]);
1225 }
1226 }
1227
Ye Li26517af2021-03-19 15:57:12 +08001228 disable_thermal_cpu_nodes(blob, disabled_cores);
1229 disable_pmu_cpu_nodes(blob, disabled_cores);
1230
Peng Fan435dc122020-07-09 14:06:49 +08001231 return 0;
1232}
1233
Peng Fana08bc872022-04-07 15:55:54 +08001234static int cleanup_nodes_for_efi(void *blob)
1235{
Peng Fan1585b202022-04-07 15:55:55 +08001236 static const char * const path[][2] = {
1237 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1238 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1239 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1240 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1241 };
Peng Fana08bc872022-04-07 15:55:54 +08001242 int nodeoff, i, rc;
1243
Peng Fan1585b202022-04-07 15:55:55 +08001244 for (i = 0; i < ARRAY_SIZE(path); i++) {
1245 nodeoff = fdt_path_offset(blob, path[i][0]);
Peng Fana08bc872022-04-07 15:55:54 +08001246 if (nodeoff < 0)
1247 continue; /* Not found, skip it */
Peng Fan1585b202022-04-07 15:55:55 +08001248 debug("Found %s node\n", path[i][0]);
Peng Fana08bc872022-04-07 15:55:54 +08001249
Peng Fan1585b202022-04-07 15:55:55 +08001250 rc = fdt_delprop(blob, nodeoff, path[i][1]);
Peng Fana08bc872022-04-07 15:55:54 +08001251 if (rc == -FDT_ERR_NOTFOUND)
1252 continue;
1253 if (rc) {
1254 printf("Unable to update property %s:%s, err=%s\n",
Peng Fan1585b202022-04-07 15:55:55 +08001255 path[i][0], path[i][1], fdt_strerror(rc));
Peng Fana08bc872022-04-07 15:55:54 +08001256 return rc;
1257 }
1258
Peng Fan1585b202022-04-07 15:55:55 +08001259 printf("Remove %s:%s\n", path[i][0], path[i][1]);
Peng Fana08bc872022-04-07 15:55:54 +08001260 }
1261
1262 return 0;
1263}
Peng Fana08bc872022-04-07 15:55:54 +08001264
Andrejs Cainikovs2f3491c2022-05-27 15:20:42 +02001265static int fixup_thermal_trips(void *blob, const char *name)
1266{
1267 int minc, maxc;
1268 int node, trip;
1269
1270 node = fdt_path_offset(blob, "/thermal-zones");
1271 if (node < 0)
1272 return node;
1273
1274 node = fdt_subnode_offset(blob, node, name);
1275 if (node < 0)
1276 return node;
1277
1278 node = fdt_subnode_offset(blob, node, "trips");
1279 if (node < 0)
1280 return node;
1281
1282 get_cpu_temp_grade(&minc, &maxc);
1283
1284 fdt_for_each_subnode(trip, blob, node) {
1285 const char *type;
1286 int temp, ret;
1287
1288 type = fdt_getprop(blob, trip, "type", NULL);
1289 if (!type)
1290 continue;
1291
1292 temp = 0;
1293 if (!strcmp(type, "critical"))
1294 temp = 1000 * maxc;
1295 else if (!strcmp(type, "passive"))
1296 temp = 1000 * (maxc - 10);
1297 if (temp) {
1298 ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1299 if (ret)
1300 return ret;
1301 }
1302 }
1303
1304 return 0;
1305}
1306
Tim Harvey709ace82023-08-24 12:05:17 -07001307#define OPTEE_SHM_SIZE 0x00400000
1308static int ft_add_optee_node(void *fdt, struct bd_info *bd)
1309{
1310 struct fdt_memory carveout;
1311 const char *path, *subpath;
1312 phys_addr_t optee_start;
1313 size_t optee_size;
1314 int offs;
1315 int ret;
1316
1317 /*
1318 * No TEE space allocated indicating no TEE running, so no
1319 * need to add optee node in dts
1320 */
1321 if (!rom_pointer[1])
1322 return 0;
1323
1324 optee_start = (phys_addr_t)rom_pointer[0];
1325 optee_size = rom_pointer[1] - OPTEE_SHM_SIZE;
1326
1327 offs = fdt_increase_size(fdt, 512);
1328 if (offs) {
1329 printf("No Space for dtb\n");
1330 return 1;
1331 }
1332
1333 path = "/firmware";
1334 offs = fdt_path_offset(fdt, path);
1335 if (offs < 0) {
1336 path = "/";
1337 offs = fdt_path_offset(fdt, path);
1338
1339 if (offs < 0) {
1340 printf("Could not find root node.\n");
1341 return offs;
1342 }
1343
1344 subpath = "firmware";
1345 offs = fdt_add_subnode(fdt, offs, subpath);
1346 if (offs < 0) {
1347 printf("Could not create %s node.\n", subpath);
1348 return offs;
1349 }
1350 }
1351
1352 subpath = "optee";
1353 offs = fdt_add_subnode(fdt, offs, subpath);
1354 if (offs < 0) {
1355 printf("Could not create %s node.\n", subpath);
1356 return offs;
1357 }
1358
1359 fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
1360 fdt_setprop_string(fdt, offs, "method", "smc");
1361
1362 carveout.start = optee_start,
1363 carveout.end = optee_start + optee_size - 1,
1364 ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout, NULL, 0,
1365 NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1366 if (ret < 0) {
1367 printf("Could not create optee_core node.\n");
1368 return ret;
1369 }
1370
1371 carveout.start = optee_start + optee_size;
1372 carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1;
1373 ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout, NULL, 0,
1374 NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1375 if (ret < 0) {
1376 printf("Could not create optee_shm node.\n");
1377 return ret;
1378 }
1379
1380 return 0;
1381}
1382
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +09001383int ft_system_setup(void *blob, struct bd_info *bd)
Peng Faneae4de22018-01-10 13:20:37 +08001384{
Peng Fan435dc122020-07-09 14:06:49 +08001385#ifdef CONFIG_IMX8MQ
Peng Faneae4de22018-01-10 13:20:37 +08001386 int i = 0;
1387 int rc;
1388 int nodeoff;
1389
Peng Fan435dc122020-07-09 14:06:49 +08001390 if (get_boot_device() == USB_BOOT) {
1391 disable_dcss_nodes(blob);
1392
1393 bool new_path = check_fdt_new_path(blob);
1394 int v = new_path ? 1 : 0;
1395 static const char * const usb_dwc3_path[] = {
1396 "/usb@38100000/dwc3",
1397 "/soc@0/usb@38100000"
1398 };
1399
1400 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1401 if (nodeoff >= 0) {
1402 const char *speed = "high-speed";
1403
Rasmus Villemoes8ab149a2023-05-22 11:27:28 +02001404 debug("Found %s node\n", usb_dwc3_path[v]);
Peng Fan435dc122020-07-09 14:06:49 +08001405
1406usb_modify_speed:
1407
1408 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1409 if (rc) {
1410 if (rc == -FDT_ERR_NOSPACE) {
1411 rc = fdt_increase_size(blob, 512);
1412 if (!rc)
1413 goto usb_modify_speed;
1414 }
1415 printf("Unable to set property %s:%s, err=%s\n",
1416 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1417 } else {
1418 printf("Modify %s:%s = %s\n",
1419 usb_dwc3_path[v], "maximum-speed", speed);
1420 }
1421 } else {
1422 printf("Can't found %s node\n", usb_dwc3_path[v]);
1423 }
1424 }
1425
Peng Faneae4de22018-01-10 13:20:37 +08001426 /* Disable the CPU idle for A0 chip since the HW does not support it */
1427 if (is_soc_rev(CHIP_REV_1_0)) {
1428 static const char * const nodes_path[] = {
1429 "/cpus/cpu@0",
1430 "/cpus/cpu@1",
1431 "/cpus/cpu@2",
1432 "/cpus/cpu@3",
1433 };
1434
1435 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1436 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1437 if (nodeoff < 0)
1438 continue; /* Not found, skip it */
1439
Marek Vasute2e7a772020-04-24 21:37:33 +02001440 debug("Found %s node\n", nodes_path[i]);
Peng Faneae4de22018-01-10 13:20:37 +08001441
1442 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
Marek Vasute2e7a772020-04-24 21:37:33 +02001443 if (rc == -FDT_ERR_NOTFOUND)
1444 continue;
Peng Faneae4de22018-01-10 13:20:37 +08001445 if (rc) {
1446 printf("Unable to update property %s:%s, err=%s\n",
1447 nodes_path[i], "status", fdt_strerror(rc));
1448 return rc;
1449 }
1450
Marek Vasute2e7a772020-04-24 21:37:33 +02001451 debug("Remove %s:%s\n", nodes_path[i],
Peng Faneae4de22018-01-10 13:20:37 +08001452 "cpu-idle-states");
1453 }
1454 }
1455
Peng Fan435dc122020-07-09 14:06:49 +08001456 if (is_imx8mql()) {
1457 disable_vpu_nodes(blob);
1458 if (check_dcss_fused()) {
1459 printf("DCSS is fused\n");
1460 disable_dcss_nodes(blob);
1461 check_mipi_dsi_nodes(blob);
1462 }
1463 }
1464
1465 if (is_imx8md())
1466 disable_cpu_nodes(blob, 2);
1467
1468#elif defined(CONFIG_IMX8MM)
1469 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
1470 disable_vpu_nodes(blob);
1471
1472 if (is_imx8mmd() || is_imx8mmdl())
1473 disable_cpu_nodes(blob, 2);
1474 else if (is_imx8mms() || is_imx8mmsl())
1475 disable_cpu_nodes(blob, 3);
1476
1477#elif defined(CONFIG_IMX8MN)
1478 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1479 disable_gpu_nodes(blob);
Ye Liee337ce2021-03-19 15:57:09 +08001480#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1481 else {
1482 int ldm_gpu = low_drive_gpu_freq(blob);
1483
1484 if (ldm_gpu < 0)
1485 printf("Update GPU node assigned-clock-rates failed\n");
1486 else
1487 printf("Update GPU node assigned-clock-rates ok\n");
1488 }
1489#endif
Peng Fan435dc122020-07-09 14:06:49 +08001490
Ye Li715180e2021-03-19 15:57:11 +08001491 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
Peng Fan435dc122020-07-09 14:06:49 +08001492 disable_cpu_nodes(blob, 2);
Ye Li715180e2021-03-19 15:57:11 +08001493 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
Peng Fan435dc122020-07-09 14:06:49 +08001494 disable_cpu_nodes(blob, 3);
1495
1496#elif defined(CONFIG_IMX8MP)
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001497 if (is_imx8mpul()) {
1498 /* Disable GPU */
1499 disable_gpu_nodes(blob);
1500
1501 /* Disable DSI */
1502 disable_dsi_lcdif_nodes(blob);
1503
1504 /* Disable LVDS */
1505 disable_lvds_lcdif_nodes(blob);
1506 }
1507
1508 if (is_imx8mpul() || is_imx8mpl())
Peng Fan435dc122020-07-09 14:06:49 +08001509 disable_vpu_nodes(blob);
1510
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001511 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
Peng Fan435dc122020-07-09 14:06:49 +08001512 disable_npu_nodes(blob);
1513
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001514 if (is_imx8mpul() || is_imx8mpl())
Peng Fan435dc122020-07-09 14:06:49 +08001515 disable_isp_nodes(blob);
1516
Peng Fanf5f9b8e2022-04-07 15:55:53 +08001517 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
Peng Fan435dc122020-07-09 14:06:49 +08001518 disable_dsp_nodes(blob);
1519
1520 if (is_imx8mpd())
1521 disable_cpu_nodes(blob, 2);
1522#endif
1523
Peng Fan1585b202022-04-07 15:55:55 +08001524 cleanup_nodes_for_efi(blob);
Andrejs Cainikovs2f3491c2022-05-27 15:20:42 +02001525
1526 if (fixup_thermal_trips(blob, "cpu-thermal"))
1527 printf("Failed to update cpu-thermal trip(s)");
1528 if (IS_ENABLED(CONFIG_IMX8MP) &&
1529 fixup_thermal_trips(blob, "soc-thermal"))
1530 printf("Failed to update soc-thermal trip(s)");
1531
Tim Harvey709ace82023-08-24 12:05:17 -07001532 return ft_add_optee_node(blob, bd);
Peng Faneae4de22018-01-10 13:20:37 +08001533}
1534#endif
1535
Marek Vasut64dc4de2020-04-29 15:04:21 +02001536#if !CONFIG_IS_ENABLED(SYSRESET)
Harald Seiler6f14d5f2020-12-15 16:47:52 +01001537void reset_cpu(void)
Peng Faneae4de22018-01-10 13:20:37 +08001538{
Claudius Heinee73f3942020-04-29 15:04:23 +02001539 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
Peng Faneae4de22018-01-10 13:20:37 +08001540
Ye Li54a915a2019-12-09 00:47:18 -08001541 /* Clear WDA to trigger WDOG_B immediately */
1542 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
Peng Fan24290d92019-08-27 06:25:41 +00001543
Ye Li54a915a2019-12-09 00:47:18 -08001544 while (1) {
1545 /*
Harald Seilerec0c4472020-04-29 15:04:22 +02001546 * spin for .5 seconds before reset
Ye Li54a915a2019-12-09 00:47:18 -08001547 */
1548 }
Peng Faneae4de22018-01-10 13:20:37 +08001549}
Peng Fan24290d92019-08-27 06:25:41 +00001550#endif
Peng Fan5760d8d2020-04-22 10:51:13 +08001551
1552#if defined(CONFIG_ARCH_MISC_INIT)
Peng Fan5760d8d2020-04-22 10:51:13 +08001553int arch_misc_init(void)
1554{
Gaurav Jain81113a02022-03-24 11:50:27 +05301555 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1556 struct udevice *dev;
1557 int ret;
1558
1559 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1560 if (ret)
Ye Liec346892022-05-11 13:56:20 +05301561 printf("Failed to initialize caam_jr: %d\n", ret);
Gaurav Jain81113a02022-03-24 11:50:27 +05301562 }
Peng Fan5760d8d2020-04-22 10:51:13 +08001563
1564 return 0;
1565}
1566#endif
Ye Li325cd012020-05-03 22:19:52 +08001567
Peng Fana35215d2020-07-09 13:39:26 +08001568#if defined(CONFIG_SPL_BUILD)
1569#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1570bool serror_need_skip = true;
1571
Sean Anderson2d755492022-03-22 17:17:35 -04001572void do_error(struct pt_regs *pt_regs)
Peng Fana35215d2020-07-09 13:39:26 +08001573{
1574 /*
1575 * If stack is still in ROM reserved OCRAM not switch to SPL,
1576 * it is the ROM SError
1577 */
1578 ulong sp;
1579
1580 asm volatile("mov %0, sp" : "=r"(sp) : );
1581
1582 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1583 /* Check for ERR050342, imx8mq HDCP enabled parts */
1584 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1585 serror_need_skip = false;
1586 return; /* Do nothing skip the SError in ROM */
1587 }
1588
1589 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1590 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1591 serror_need_skip = false;
1592 return; /* Do nothing skip the SError in ROM */
1593 }
1594 }
1595
1596 efi_restore_gd();
Sean Anderson2d755492022-03-22 17:17:35 -04001597 printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
Peng Fana35215d2020-07-09 13:39:26 +08001598 show_regs(pt_regs);
1599 panic("Resetting CPU ...\n");
1600}
1601#endif
1602#endif
Ye Li0513f362019-07-15 01:16:46 -07001603
1604#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
Marek Vasut765b5802022-04-06 02:21:34 +02001605enum env_location arch_env_get_location(enum env_operation op, int prio)
Ye Li0513f362019-07-15 01:16:46 -07001606{
1607 enum boot_device dev = get_boot_device();
Ye Li0513f362019-07-15 01:16:46 -07001608
1609 if (prio)
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001610 return ENVL_UNKNOWN;
Ye Li0513f362019-07-15 01:16:46 -07001611
1612 switch (dev) {
Fabio Estevam9be6daf2022-04-21 15:05:23 -03001613 case USB_BOOT:
1614 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1615 return ENVL_SPI_FLASH;
1616 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1617 return ENVL_NAND;
1618 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1619 return ENVL_MMC;
1620 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1621 return ENVL_NOWHERE;
1622 return ENVL_UNKNOWN;
Ye Li0513f362019-07-15 01:16:46 -07001623 case QSPI_BOOT:
Marek Vasut31b3bc42022-03-25 18:59:28 +01001624 case SPI_NOR_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001625 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1626 return ENVL_SPI_FLASH;
1627 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001628 case NAND_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001629 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1630 return ENVL_NAND;
1631 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001632 case SD1_BOOT:
1633 case SD2_BOOT:
1634 case SD3_BOOT:
1635 case MMC1_BOOT:
1636 case MMC2_BOOT:
1637 case MMC3_BOOT:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001638 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1639 return ENVL_MMC;
1640 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1641 return ENVL_EXT4;
1642 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1643 return ENVL_FAT;
1644 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001645 default:
Ricardo Salveti1daf63f2021-10-20 16:16:26 -03001646 return ENVL_NOWHERE;
Ye Li0513f362019-07-15 01:16:46 -07001647 }
Ye Li0513f362019-07-15 01:16:46 -07001648}
1649
Ye Li0513f362019-07-15 01:16:46 -07001650#endif
Peng Fanf19e0e52022-04-29 16:03:14 +08001651
1652#ifdef CONFIG_IMX_BOOTAUX
1653const struct rproc_att hostmap[] = {
1654 /* aux core , host core, size */
1655 { 0x00000000, 0x007e0000, 0x00020000 },
1656 /* OCRAM_S */
1657 { 0x00180000, 0x00180000, 0x00008000 },
1658 /* OCRAM */
1659 { 0x00900000, 0x00900000, 0x00020000 },
1660 /* OCRAM */
1661 { 0x00920000, 0x00920000, 0x00020000 },
1662 /* QSPI Code - alias */
1663 { 0x08000000, 0x08000000, 0x08000000 },
1664 /* DDR (Code) - alias */
1665 { 0x10000000, 0x80000000, 0x0FFE0000 },
1666 /* TCML */
1667 { 0x1FFE0000, 0x007E0000, 0x00040000 },
1668 /* OCRAM_S */
1669 { 0x20180000, 0x00180000, 0x00008000 },
1670 /* OCRAM */
1671 { 0x20200000, 0x00900000, 0x00040000 },
1672 /* DDR (Data) */
1673 { 0x40000000, 0x40000000, 0x80000000 },
1674 { /* sentinel */ }
1675};
Marek Vasutddc59352022-12-13 05:46:07 +01001676
1677const struct rproc_att *imx_bootaux_get_hostmap(void)
1678{
1679 return hostmap;
1680}
Peng Fanf19e0e52022-04-29 16:03:14 +08001681#endif