Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2017 NXP |
| 4 | * |
| 5 | * Peng Fan <peng.fan@nxp.com> |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/arch/imx-regs.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/sys_proto.h> |
| 13 | #include <asm/mach-imx/hab.h> |
| 14 | #include <asm/mach-imx/boot_mode.h> |
| 15 | #include <asm/mach-imx/syscounter.h> |
| 16 | #include <asm/armv8/mmu.h> |
| 17 | #include <errno.h> |
| 18 | #include <fdt_support.h> |
| 19 | #include <fsl_wdog.h> |
| 20 | #include <imx_sip.h> |
| 21 | |
| 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
| 24 | #if defined(CONFIG_SECURE_BOOT) |
| 25 | struct imx_sec_config_fuse_t const imx_sec_config_fuse = { |
| 26 | .bank = 1, |
| 27 | .word = 3, |
| 28 | }; |
| 29 | #endif |
| 30 | |
| 31 | int timer_init(void) |
| 32 | { |
| 33 | #ifdef CONFIG_SPL_BUILD |
| 34 | struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR; |
| 35 | unsigned long freq = readl(&sctr->cntfid0); |
| 36 | |
| 37 | /* Update with accurate clock frequency */ |
| 38 | asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory"); |
| 39 | |
| 40 | clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1, |
| 41 | SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG); |
| 42 | #endif |
| 43 | |
| 44 | gd->arch.tbl = 0; |
| 45 | gd->arch.tbu = 0; |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | void enable_tzc380(void) |
| 51 | { |
| 52 | struct iomuxc_gpr_base_regs *gpr = |
| 53 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 54 | |
| 55 | /* Enable TZASC and lock setting */ |
| 56 | setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); |
| 57 | setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); |
Peng Fan | 99047fc | 2019-08-27 06:25:30 +0000 | [diff] [blame] | 58 | if (IS_ENABLED(CONFIG_IMX8MM)) |
| 59 | setbits_le32(&gpr->gpr[10], BIT(1)); |
Ye Li | 4c97c46 | 2019-08-27 06:25:34 +0000 | [diff] [blame] | 60 | /* |
| 61 | * set Region 0 attribute to allow secure and non-secure |
| 62 | * read/write permission. Found some masters like usb dwc3 |
| 63 | * controllers can't work with secure memory. |
| 64 | */ |
| 65 | writel(0xf0000000, TZASC_BASE_ADDR + 0x108); |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | void set_wdog_reset(struct wdog_regs *wdog) |
| 69 | { |
| 70 | /* |
| 71 | * Output WDOG_B signal to reset external pmic or POR_B decided by |
| 72 | * the board design. Without external reset, the peripherals/DDR/ |
| 73 | * PMIC are not reset, that may cause system working abnormal. |
| 74 | * WDZST bit is write-once only bit. Align this bit in kernel, |
| 75 | * otherwise kernel code will have no chance to set this bit. |
| 76 | */ |
| 77 | setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK); |
| 78 | } |
| 79 | |
| 80 | static struct mm_region imx8m_mem_map[] = { |
| 81 | { |
| 82 | /* ROM */ |
| 83 | .virt = 0x0UL, |
| 84 | .phys = 0x0UL, |
| 85 | .size = 0x100000UL, |
| 86 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 87 | PTE_BLOCK_OUTER_SHARE |
| 88 | }, { |
Gary Bisson | 5c72a45 | 2018-11-14 17:55:28 +0100 | [diff] [blame] | 89 | /* CAAM */ |
| 90 | .virt = 0x100000UL, |
| 91 | .phys = 0x100000UL, |
| 92 | .size = 0x8000UL, |
| 93 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 94 | PTE_BLOCK_NON_SHARE | |
| 95 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 96 | }, { |
| 97 | /* TCM */ |
| 98 | .virt = 0x7C0000UL, |
| 99 | .phys = 0x7C0000UL, |
| 100 | .size = 0x80000UL, |
| 101 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 102 | PTE_BLOCK_NON_SHARE | |
| 103 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 104 | }, { |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 105 | /* OCRAM */ |
| 106 | .virt = 0x900000UL, |
| 107 | .phys = 0x900000UL, |
| 108 | .size = 0x200000UL, |
| 109 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 110 | PTE_BLOCK_OUTER_SHARE |
| 111 | }, { |
| 112 | /* AIPS */ |
| 113 | .virt = 0xB00000UL, |
| 114 | .phys = 0xB00000UL, |
| 115 | .size = 0x3f500000UL, |
| 116 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 117 | PTE_BLOCK_NON_SHARE | |
| 118 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 119 | }, { |
| 120 | /* DRAM1 */ |
| 121 | .virt = 0x40000000UL, |
| 122 | .phys = 0x40000000UL, |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 123 | .size = PHYS_SDRAM_SIZE, |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 124 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 125 | PTE_BLOCK_OUTER_SHARE |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 126 | #ifdef PHYS_SDRAM_2_SIZE |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 127 | }, { |
| 128 | /* DRAM2 */ |
| 129 | .virt = 0x100000000UL, |
| 130 | .phys = 0x100000000UL, |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 131 | .size = PHYS_SDRAM_2_SIZE, |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 132 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 133 | PTE_BLOCK_OUTER_SHARE |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 134 | #endif |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 135 | }, { |
| 136 | /* List terminator */ |
| 137 | 0, |
| 138 | } |
| 139 | }; |
| 140 | |
| 141 | struct mm_region *mem_map = imx8m_mem_map; |
| 142 | |
Peng Fan | b749b5e | 2019-08-27 06:25:27 +0000 | [diff] [blame] | 143 | void enable_caches(void) |
| 144 | { |
| 145 | /* |
| 146 | * If OPTEE runs, remove OPTEE memory from MMU table to |
| 147 | * avoid speculative prefetch. OPTEE runs at the top of |
| 148 | * the first memory bank |
| 149 | */ |
| 150 | if (rom_pointer[1]) |
| 151 | imx8m_mem_map[5].size -= rom_pointer[1]; |
| 152 | |
| 153 | icache_enable(); |
| 154 | dcache_enable(); |
| 155 | } |
| 156 | |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 157 | static u32 get_cpu_variant_type(u32 type) |
| 158 | { |
| 159 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 160 | struct fuse_bank *bank = &ocotp->bank[1]; |
| 161 | struct fuse_bank1_regs *fuse = |
| 162 | (struct fuse_bank1_regs *)bank->fuse_regs; |
| 163 | |
| 164 | u32 value = readl(&fuse->tester4); |
| 165 | |
| 166 | if (type == MXC_CPU_IMX8MM) { |
| 167 | switch (value & 0x3) { |
| 168 | case 2: |
| 169 | if (value & 0x1c0000) |
| 170 | return MXC_CPU_IMX8MMDL; |
| 171 | else |
| 172 | return MXC_CPU_IMX8MMD; |
| 173 | case 3: |
| 174 | if (value & 0x1c0000) |
| 175 | return MXC_CPU_IMX8MMSL; |
| 176 | else |
| 177 | return MXC_CPU_IMX8MMS; |
| 178 | default: |
| 179 | if (value & 0x1c0000) |
| 180 | return MXC_CPU_IMX8MML; |
| 181 | break; |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | return type; |
| 186 | } |
| 187 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 188 | u32 get_cpu_rev(void) |
| 189 | { |
| 190 | struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; |
| 191 | u32 reg = readl(&ana_pll->digprog); |
| 192 | u32 type = (reg >> 16) & 0xff; |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 193 | u32 major_low = (reg >> 8) & 0xff; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 194 | u32 rom_version; |
| 195 | |
| 196 | reg &= 0xff; |
| 197 | |
Peng Fan | 1caffdf | 2019-08-27 06:25:17 +0000 | [diff] [blame] | 198 | /* i.MX8MM */ |
| 199 | if (major_low == 0x41) { |
| 200 | type = get_cpu_variant_type(MXC_CPU_IMX8MM); |
| 201 | } else { |
| 202 | if (reg == CHIP_REV_1_0) { |
| 203 | /* |
| 204 | * For B0 chip, the DIGPROG is not updated, still TO1.0. |
| 205 | * we have to check ROM version further |
| 206 | */ |
| 207 | rom_version = readl((void __iomem *)ROM_VERSION_A0); |
| 208 | if (rom_version != CHIP_REV_1_0) { |
| 209 | rom_version = readl((void __iomem *)ROM_VERSION_B0); |
| 210 | if (rom_version >= CHIP_REV_2_0) |
| 211 | reg = CHIP_REV_2_0; |
| 212 | } |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 213 | } |
| 214 | } |
| 215 | |
| 216 | return (type << 12) | reg; |
| 217 | } |
| 218 | |
| 219 | static void imx_set_wdog_powerdown(bool enable) |
| 220 | { |
| 221 | struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 222 | struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; |
| 223 | struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; |
| 224 | |
| 225 | /* Write to the PDE (Power Down Enable) bit */ |
| 226 | writew(enable, &wdog1->wmcr); |
| 227 | writew(enable, &wdog2->wmcr); |
| 228 | writew(enable, &wdog3->wmcr); |
| 229 | } |
| 230 | |
| 231 | int arch_cpu_init(void) |
| 232 | { |
Peng Fan | c0b30d7 | 2019-04-17 09:41:16 +0000 | [diff] [blame] | 233 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 234 | /* |
Peng Fan | d0ca289 | 2019-08-27 06:25:37 +0000 | [diff] [blame^] | 235 | * ROM might disable clock for SCTR, |
| 236 | * enable the clock before timer_init. |
| 237 | */ |
| 238 | if (IS_ENABLED(CONFIG_SPL_BUILD)) |
| 239 | clock_enable(CCGR_SCTR, 1); |
| 240 | /* |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 241 | * Init timer at very early state, because sscg pll setting |
| 242 | * will use it |
| 243 | */ |
| 244 | timer_init(); |
| 245 | |
| 246 | if (IS_ENABLED(CONFIG_SPL_BUILD)) { |
| 247 | clock_init(); |
| 248 | imx_set_wdog_powerdown(false); |
| 249 | } |
| 250 | |
Peng Fan | c0b30d7 | 2019-04-17 09:41:16 +0000 | [diff] [blame] | 251 | if (is_imx8mq()) { |
| 252 | clock_enable(CCGR_OCOTP, 1); |
| 253 | if (readl(&ocotp->ctrl) & 0x200) |
| 254 | writel(0x200, &ocotp->ctrl_clr); |
| 255 | } |
| 256 | |
Peng Fan | eae4de2 | 2018-01-10 13:20:37 +0800 | [diff] [blame] | 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | bool is_usb_boot(void) |
| 261 | { |
| 262 | return get_boot_device() == USB_BOOT; |
| 263 | } |
| 264 | |
| 265 | #ifdef CONFIG_OF_SYSTEM_SETUP |
| 266 | int ft_system_setup(void *blob, bd_t *bd) |
| 267 | { |
| 268 | int i = 0; |
| 269 | int rc; |
| 270 | int nodeoff; |
| 271 | |
| 272 | /* Disable the CPU idle for A0 chip since the HW does not support it */ |
| 273 | if (is_soc_rev(CHIP_REV_1_0)) { |
| 274 | static const char * const nodes_path[] = { |
| 275 | "/cpus/cpu@0", |
| 276 | "/cpus/cpu@1", |
| 277 | "/cpus/cpu@2", |
| 278 | "/cpus/cpu@3", |
| 279 | }; |
| 280 | |
| 281 | for (i = 0; i < ARRAY_SIZE(nodes_path); i++) { |
| 282 | nodeoff = fdt_path_offset(blob, nodes_path[i]); |
| 283 | if (nodeoff < 0) |
| 284 | continue; /* Not found, skip it */ |
| 285 | |
| 286 | printf("Found %s node\n", nodes_path[i]); |
| 287 | |
| 288 | rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); |
| 289 | if (rc) { |
| 290 | printf("Unable to update property %s:%s, err=%s\n", |
| 291 | nodes_path[i], "status", fdt_strerror(rc)); |
| 292 | return rc; |
| 293 | } |
| 294 | |
| 295 | printf("Remove %s:%s\n", nodes_path[i], |
| 296 | "cpu-idle-states"); |
| 297 | } |
| 298 | } |
| 299 | |
| 300 | return 0; |
| 301 | } |
| 302 | #endif |
| 303 | |
| 304 | void reset_cpu(ulong addr) |
| 305 | { |
| 306 | struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; |
| 307 | |
| 308 | /* Clear WDA to trigger WDOG_B immediately */ |
| 309 | writew((WCR_WDE | WCR_SRS), &wdog->wcr); |
| 310 | |
| 311 | while (1) { |
| 312 | /* |
| 313 | * spin for .5 seconds before reset |
| 314 | */ |
| 315 | } |
| 316 | } |