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git01.mediatek.com / filogic / uboot / ed2724bba86823df712326f3ade7bbe41d7601c7 / . / arch / arm / dts / imx8mm-venice-gw7902-u-boot.dtsi
blob: d58a7d14b6317b78546ab16684fa4d435ddcdb36 [file] [log] [blame]
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
Tim Harveyb2da6972021-08-24 12:04:01 -0700[diff] [blame]6#include "imx8mm-venice-u-boot.dtsi"
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]7
Tim Harveya5953f92022-04-13 09:02:44 -0700[diff] [blame]8&gpio1 {
Tim Harvey3cce59e2022-11-11 07:55:46 -0800[diff] [blame]9 m2pwren {
10 gpio-hog;
11 output-low;
12 gpios = <8 GPIO_ACTIVE_HIGH>;
13 line-name = "m2_pwren";
14 };
15
Tim Harveya5953f92022-04-13 09:02:44 -0700[diff] [blame]16 m2rst {
17 gpio-hog;
18 output-low;
19 gpios = <13 GPIO_ACTIVE_HIGH>;
20 line-name = "m2_reset";
21 };
22
23 m2wdis {
24 gpio-hog;
25 output-high;
26 gpios = <15 GPIO_ACTIVE_HIGH>;
27 line-name = "m2_wdis#";
28 };
29};
30
31&gpio2 {
32 uart2en {
33 gpio-hog;
34 output-high;
35 gpios = <8 GPIO_ACTIVE_HIGH>;
36 line-name = "uart2_en#";
37 };
38};
39
40&gpio3 {
41 m2gdis {
42 gpio-hog;
43 output-high;
44 gpios = <1 GPIO_ACTIVE_HIGH>;
45 line-name = "m2_gdis#";
46 };
47
48 m2off {
49 gpio-hog;
50 output-high;
51 gpios = <7 GPIO_ACTIVE_HIGH>;
52 line-name = "m2_off#";
53 };
54};
55
56&gpio4 {
57 ampgpio3 {
58 gpio-hog;
59 input;
60 gpios = <11 GPIO_ACTIVE_HIGH>;
61 line-name = "amp_gpio3";
62 };
63
64 ampgpio2 {
65 gpio-hog;
66 input;
67 gpios = <12 GPIO_ACTIVE_HIGH>;
68 line-name = "amp_gpio2";
69 };
70
71 ampgpio1 {
72 gpio-hog;
73 input;
74 gpios = <14 GPIO_ACTIVE_HIGH>;
75 line-name = "amp_gpio1";
76 };
77
78 ltrpwr {
79 gpio-hog;
80 output-low;
81 gpios = <16 GPIO_ACTIVE_HIGH>;
82 line-name = "lte_pwr#";
83 };
84
85 lterst {
86 gpio-hog;
87 output-low;
88 gpios = <17 GPIO_ACTIVE_HIGH>;
89 line-name = "lte_rst";
90 };
91
92 ampgpio4 {
93 gpio-hog;
94 input;
95 gpios = <20 GPIO_ACTIVE_HIGH>;
96 line-name = "amp_gpio4";
97 };
98
99 appgpio1 {
100 gpio-hog;
101 input;
102 gpios = <21 GPIO_ACTIVE_HIGH>;
103 line-name = "app_gpio1";
104 };
105
Tim Harvey3cce59e2022-11-11 07:55:46 -0800[diff] [blame]106 vdd4p0en {
107 gpio-hog;
108 output-low;
109 gpios = <22 GPIO_ACTIVE_HIGH>;
110 line-name = "vdd_4p0_en";
111 };
112
Tim Harveya5953f92022-04-13 09:02:44 -0700[diff] [blame]113 uart1rs485 {
114 gpio-hog;
115 output-low;
116 gpios = <23 GPIO_ACTIVE_HIGH>;
117 line-name = "uart1_rs485";
118 };
119
120 uart1term {
121 gpio-hog;
122 output-low;
123 gpios = <25 GPIO_ACTIVE_HIGH>;
124 line-name = "uart1_term";
125 };
126
127 uart1half {
128 gpio-hog;
129 output-low;
130 gpios = <26 GPIO_ACTIVE_HIGH>;
131 line-name = "uart1_half";
132 };
133
134 appgpio2 {
135 gpio-hog;
136 input;
137 gpios = <27 GPIO_ACTIVE_HIGH>;
138 line-name = "app_gpio2";
139 };
140
141 mipigpio1 {
142 gpio-hog;
143 input;
144 gpios = <28 GPIO_ACTIVE_HIGH>;
145 line-name = "mipi_gpio1";
146 };
147};
148
149&gpio5 {
150 mipigpio4 {
151 gpio-hog;
152 input;
153 gpios = <3 GPIO_ACTIVE_HIGH>;
154 line-name = "mipi_gpio4";
155 };
156
157 mipigpio3 {
158 gpio-hog;
159 input;
160 gpios = <4 GPIO_ACTIVE_HIGH>;
161 line-name = "mipi_gpio3";
162 };
163
164 mipigpio2 {
165 gpio-hog;
166 input;
167 gpios = <5 GPIO_ACTIVE_HIGH>;
168 line-name = "mipi_gpio2";
169 };
170};
171
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]172&fec1 {
173 phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
174 phy-reset-duration = <1>;
Tim Harvey3c436182022-04-13 09:09:49 -0700[diff] [blame]175 phy-reset-post-delay = <300>;
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]176};
177
178&pinctrl_fec1 {
179 u-boot,dm-spl;
180};
181
182&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
183 u-boot,dm-spl;
184};
185
186&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
187 u-boot,dm-spl;
188};
189
190&pinctrl_pmic {
191 u-boot,dm-spl;
192};