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git01.mediatek.com / filogic / uboot / ec2d7edcbcd5616dff727b0468517b67070d310d / . / arch / arm / mach-uniphier / memconf / memconf.c
blob: e607ac9c3ba4b62e54411f1932fad947348d3c18 [file] [log] [blame]
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]1/*
Masahiro Yamadaf5325822016-12-05 18:31:36 +0900[diff] [blame]2 * Copyright (C) 2011-2015 Panasonic Corporation
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/sizes.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +0900[diff] [blame]13
14#include "../init.h"
15#include "../sg-regs.h"
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]16
17int memconf_init(const struct uniphier_board_data *bd)
18{
Masahiro Yamadaf5325822016-12-05 18:31:36 +0900[diff] [blame]19 u32 tmp;
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]20 unsigned long size_per_word;
21
22 tmp = readl(SG_MEMCONF);
23
24 tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
25
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]26 switch (bd->dram_ch[0].width) {
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]27 case 16:
28 tmp |= SG_MEMCONF_CH0_NUM_1;
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]29 size_per_word = bd->dram_ch[0].size;
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]30 break;
31 case 32:
32 tmp |= SG_MEMCONF_CH0_NUM_2;
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]33 size_per_word = bd->dram_ch[0].size >> 1;
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]34 break;
35 default:
36 pr_err("error: unsupported DRAM Ch0 width\n");
37 return -EINVAL;
38 }
39
40 /* Set DDR size */
41 switch (size_per_word) {
42 case SZ_64M:
43 tmp |= SG_MEMCONF_CH0_SZ_64M;
44 break;
45 case SZ_128M:
46 tmp |= SG_MEMCONF_CH0_SZ_128M;
47 break;
48 case SZ_256M:
49 tmp |= SG_MEMCONF_CH0_SZ_256M;
50 break;
51 case SZ_512M:
52 tmp |= SG_MEMCONF_CH0_SZ_512M;
53 break;
54 case SZ_1G:
55 tmp |= SG_MEMCONF_CH0_SZ_1G;
56 break;
57 default:
58 pr_err("error: unsupported DRAM Ch0 size\n");
59 return -EINVAL;
60 }
61
62 tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
63
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]64 switch (bd->dram_ch[1].width) {
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]65 case 16:
66 tmp |= SG_MEMCONF_CH1_NUM_1;
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]67 size_per_word = bd->dram_ch[1].size;
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]68 break;
69 case 32:
70 tmp |= SG_MEMCONF_CH1_NUM_2;
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]71 size_per_word = bd->dram_ch[1].size >> 1;
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]72 break;
73 default:
74 pr_err("error: unsupported DRAM Ch1 width\n");
75 return -EINVAL;
76 }
77
78 switch (size_per_word) {
79 case SZ_64M:
80 tmp |= SG_MEMCONF_CH1_SZ_64M;
81 break;
82 case SZ_128M:
83 tmp |= SG_MEMCONF_CH1_SZ_128M;
84 break;
85 case SZ_256M:
86 tmp |= SG_MEMCONF_CH1_SZ_256M;
87 break;
88 case SZ_512M:
89 tmp |= SG_MEMCONF_CH1_SZ_512M;
90 break;
91 case SZ_1G:
92 tmp |= SG_MEMCONF_CH1_SZ_1G;
93 break;
94 default:
95 pr_err("error: unsupported DRAM Ch1 size\n");
96 return -EINVAL;
97 }
98
Masahiro Yamada799e6f22016-02-26 14:21:34 +0900[diff] [blame]99 if (bd->dram_ch[0].base + bd->dram_ch[0].size < bd->dram_ch[1].base)
Masahiro Yamada75f16f82015-09-22 00:27:39 +0900[diff] [blame]100 tmp |= SG_MEMCONF_SPARSEMEM;
101 else
102 tmp &= ~SG_MEMCONF_SPARSEMEM;
103
104 writel(tmp, SG_MEMCONF);
105
106 return 0;
107}