ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
new file mode 100644
index 0000000..d490736
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp = 0;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
+
+ switch (bd->dram_ch0_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH0_NUM_1;
+ size_per_word = bd->dram_ch0_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH0_NUM_2;
+ size_per_word = bd->dram_ch0_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH0_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH0_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH0_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH0_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH0_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 size\n");
+ return -EINVAL;
+ }
+
+ tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
+
+ switch (bd->dram_ch1_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH1_NUM_1;
+ size_per_word = bd->dram_ch1_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH1_NUM_2;
+ size_per_word = bd->dram_ch1_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH1_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH1_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH1_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH1_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH1_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 size\n");
+ return -EINVAL;
+ }
+
+ if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
+ tmp |= SG_MEMCONF_SPARSEMEM;
+ else
+ tmp &= ~SG_MEMCONF_SPARSEMEM;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}