blob: 2f1b00e1ab4fb0ef3a45da6279799bc6541b6c16 [file] [log] [blame]
wdenk0aeb8532004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
wdenk0aeb8532004-10-10 21:21:55 +000023#include <common.h>
24#include <pci.h>
25#include <asm/processor.h>
26#include <asm/immap_85xx.h>
Wolfgang Denkcd0bf802005-07-21 16:14:36 +020027#include <ioports.h>
wdenk0aeb8532004-10-10 21:21:55 +000028#include <spd.h>
29
30#include "../common/cadmus.h"
31#include "../common/eeprom.h"
Matthew McClintock3b662012006-06-28 10:46:13 -050032#include "../common/via.h"
wdenk0aeb8532004-10-10 21:21:55 +000033
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050034#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0aeb8532004-10-10 21:21:55 +000035extern void ddr_enable_ecc(unsigned int dram_size);
36#endif
37
38extern long int spd_sdram(void);
39
40void local_bus_init(void);
41void sdram_init(void);
42
Wolfgang Denkcd0bf802005-07-21 16:14:36 +020043/*
44 * I/O Port configuration table
45 *
46 * if conf is 1, then that port pin will be configured at boot time
47 * according to the five values podr/pdir/ppar/psor/pdat for that entry
48 */
49
50const iop_conf_t iop_conf_tab[4][32] = {
51
52 /* Port A configuration */
53 { /* conf ppar psor pdir podr pdat */
54 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
55 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
56 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
57 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
58 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
59 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
60 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
61 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
62 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
63 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
64 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
65 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
66 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
67 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
68 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
69 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
70 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
71 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
72 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
73 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
74 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
75 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
76 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
77 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
78 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
79 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
80 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
81 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
82 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
83 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
84 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
85 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
86 },
87
88 /* Port B configuration */
89 { /* conf ppar psor pdir podr pdat */
90 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
91 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
92 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
93 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
94 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
95 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
96 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
97 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
98 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
99 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
100 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
101 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
102 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
103 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
104 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
105 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
106 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
107 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
108 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
109 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
110 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
111 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
112 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
113 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
114 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
115 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
116 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
117 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
118 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
119 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
120 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
121 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
122 },
123
124 /* Port C */
125 { /* conf ppar psor pdir podr pdat */
126 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
127 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
128 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
129 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
130 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
131 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
132 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
133 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
134 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
135 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
136 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
137 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
138 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
139 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
140 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
141 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
142 /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
143 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
144 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
145 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
146 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
147 /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
148 /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
149 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
150 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
151 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
152 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
153 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
154 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
155 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
156 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
157 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
158 },
159
160 /* Port D */
161 { /* conf ppar psor pdir podr pdat */
162 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
163 /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
164 /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
165 /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
166 /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
167 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
168 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
169 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
170 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
171 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
172 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
173 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
174 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
175 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
176 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
177 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
178 /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
179 /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
180 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
181 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
182 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
183 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
184 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
185 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
186 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
187 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
188 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
189 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
190 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
191 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
192 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
193 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
194 }
195};
196
wdenkef3386f2004-10-10 21:27:30 +0000197int board_early_init_f (void)
wdenk0aeb8532004-10-10 21:21:55 +0000198{
wdenkef3386f2004-10-10 21:27:30 +0000199 return 0;
wdenk0aeb8532004-10-10 21:21:55 +0000200}
201
wdenkef3386f2004-10-10 21:27:30 +0000202int checkboard (void)
wdenk0aeb8532004-10-10 21:21:55 +0000203{
Kumar Galaec1340d2007-11-27 23:25:02 -0600204 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000205
wdenkef3386f2004-10-10 21:27:30 +0000206 /* PCI slot in USER bits CSR[6:7] by convention. */
207 uint pci_slot = get_pci_slot ();
wdenk0aeb8532004-10-10 21:21:55 +0000208
wdenkef3386f2004-10-10 21:27:30 +0000209 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
210 uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
211 uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
212 uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
wdenk0aeb8532004-10-10 21:21:55 +0000213
wdenkef3386f2004-10-10 21:27:30 +0000214 uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
wdenk0aeb8532004-10-10 21:21:55 +0000215
wdenkef3386f2004-10-10 21:27:30 +0000216 uint cpu_board_rev = get_cpu_board_revision ();
wdenk0aeb8532004-10-10 21:21:55 +0000217
wdenkef3386f2004-10-10 21:27:30 +0000218 printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
219 get_board_version (), pci_slot);
wdenk0aeb8532004-10-10 21:21:55 +0000220
wdenkef3386f2004-10-10 21:27:30 +0000221 printf ("CPU Board Revision %d.%d (0x%04x)\n",
222 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
223 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
wdenk0aeb8532004-10-10 21:21:55 +0000224
wdenkef3386f2004-10-10 21:27:30 +0000225 printf (" PCI1: %d bit, %s MHz, %s\n",
226 (pci1_32) ? 32 : 64,
227 (pci1_speed == 33000000) ? "33" :
228 (pci1_speed == 66000000) ? "66" : "unknown",
229 pci1_clk_sel ? "sync" : "async");
wdenk0aeb8532004-10-10 21:21:55 +0000230
wdenkef3386f2004-10-10 21:27:30 +0000231 if (pci_dual) {
232 printf (" PCI2: 32 bit, 66 MHz, %s\n",
233 pci2_clk_sel ? "sync" : "async");
234 } else {
235 printf (" PCI2: disabled\n");
236 }
wdenk0aeb8532004-10-10 21:21:55 +0000237
wdenkef3386f2004-10-10 21:27:30 +0000238 /*
239 * Initialize local bus.
240 */
241 local_bus_init ();
wdenk0aeb8532004-10-10 21:21:55 +0000242
wdenkef3386f2004-10-10 21:27:30 +0000243 return 0;
wdenk0aeb8532004-10-10 21:21:55 +0000244}
245
wdenk0aeb8532004-10-10 21:21:55 +0000246long int
247initdram(int board_type)
248{
249 long dram_size = 0;
wdenk0aeb8532004-10-10 21:21:55 +0000250
251 puts("Initializing\n");
252
253#if defined(CONFIG_DDR_DLL)
254 {
255 /*
256 * Work around to stabilize DDR DLL MSYNC_IN.
257 * Errata DDR9 seems to have been fixed.
258 * This is now the workaround for Errata DDR11:
259 * Override DLL = 1, Course Adj = 1, Tap Select = 0
260 */
261
Kumar Galaec1340d2007-11-27 23:25:02 -0600262 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000263
264 gur->ddrdllcr = 0x81000000;
265 asm("sync;isync;msync");
266 udelay(200);
267 }
268#endif
wdenk0aeb8532004-10-10 21:21:55 +0000269 dram_size = spd_sdram();
270
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500271#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
wdenk0aeb8532004-10-10 21:21:55 +0000272 /*
273 * Initialize and enable DDR ECC.
274 */
275 ddr_enable_ecc(dram_size);
276#endif
wdenk0aeb8532004-10-10 21:21:55 +0000277 /*
278 * SDRAM Initialization
279 */
280 sdram_init();
281
282 puts(" DDR: ");
283 return dram_size;
284}
285
wdenk0aeb8532004-10-10 21:21:55 +0000286/*
287 * Initialize Local Bus
288 */
wdenk0aeb8532004-10-10 21:21:55 +0000289void
290local_bus_init(void)
291{
292 volatile immap_t *immap = (immap_t *)CFG_IMMR;
Kumar Galaec1340d2007-11-27 23:25:02 -0600293 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
wdenk0aeb8532004-10-10 21:21:55 +0000294 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
295
296 uint clkdiv;
297 uint lbc_hz;
298 sys_info_t sysinfo;
299 uint temp_lbcdll;
300
301 /*
302 * Errata LBC11.
303 * Fix Local Bus clock glitch when DLL is enabled.
304 *
305 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
306 * If localbus freq is > 133Mhz, DLL can be safely enabled.
307 * Between 66 and 133, the DLL is enabled with an override workaround.
308 */
309
310 get_sys_info(&sysinfo);
311 clkdiv = lbc->lcrr & 0x0f;
312 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
313
314 if (lbc_hz < 66) {
315 lbc->lcrr |= 0x80000000; /* DLL Bypass */
316
317 } else if (lbc_hz >= 133) {
318 lbc->lcrr &= (~0x80000000); /* DLL Enabled */
319
320 } else {
321 lbc->lcrr &= (~0x8000000); /* DLL Enabled */
322 udelay(200);
323
324 /*
325 * Sample LBC DLL ctrl reg, upshift it to set the
326 * override bits.
327 */
328 temp_lbcdll = gur->lbcdllcr;
329 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
330 asm("sync;isync;msync");
331 }
332}
333
wdenk0aeb8532004-10-10 21:21:55 +0000334/*
335 * Initialize SDRAM memory on the Local Bus.
336 */
wdenk0aeb8532004-10-10 21:21:55 +0000337void
338sdram_init(void)
339{
340#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
341
342 uint idx;
343 volatile immap_t *immap = (immap_t *)CFG_IMMR;
344 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
345 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
346 uint cpu_board_rev;
347 uint lsdmr_common;
348
349 puts(" SDRAM: ");
350
351 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
352
353 /*
354 * Setup SDRAM Base and Option Registers
355 */
356 lbc->or2 = CFG_OR2_PRELIM;
357 asm("msync");
358
359 lbc->br2 = CFG_BR2_PRELIM;
360 asm("msync");
361
362 lbc->lbcr = CFG_LBC_LBCR;
363 asm("msync");
364
wdenk0aeb8532004-10-10 21:21:55 +0000365 lbc->lsrt = CFG_LBC_LSRT;
366 lbc->mrtpr = CFG_LBC_MRTPR;
367 asm("msync");
368
369 /*
370 * Determine which address lines to use baed on CPU board rev.
371 */
372 cpu_board_rev = get_cpu_board_revision();
373 lsdmr_common = CFG_LBC_LSDMR_COMMON;
374 if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
375 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
376 } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
377 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
378 } else {
379 /*
380 * Assume something unable to identify itself is
381 * really old, and likely has lines 16/17 mapped.
382 */
383 lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
384 }
385
386 /*
387 * Issue PRECHARGE ALL command.
388 */
389 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
390 asm("sync;msync");
391 *sdram_addr = 0xff;
392 ppcDcbf((unsigned long) sdram_addr);
393 udelay(100);
394
395 /*
396 * Issue 8 AUTO REFRESH commands.
397 */
398 for (idx = 0; idx < 8; idx++) {
399 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
400 asm("sync;msync");
401 *sdram_addr = 0xff;
402 ppcDcbf((unsigned long) sdram_addr);
403 udelay(100);
404 }
405
406 /*
407 * Issue 8 MODE-set command.
408 */
409 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
410 asm("sync;msync");
411 *sdram_addr = 0xff;
412 ppcDcbf((unsigned long) sdram_addr);
413 udelay(100);
414
415 /*
416 * Issue NORMAL OP command.
417 */
418 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
419 asm("sync;msync");
420 *sdram_addr = 0xff;
421 ppcDcbf((unsigned long) sdram_addr);
422 udelay(200); /* Overkill. Must wait > 200 bus cycles */
423
424#endif /* enable SDRAM init */
425}
426
wdenk0aeb8532004-10-10 21:21:55 +0000427#if defined(CFG_DRAM_TEST)
428int
429testdram(void)
430{
431 uint *pstart = (uint *) CFG_MEMTEST_START;
432 uint *pend = (uint *) CFG_MEMTEST_END;
433 uint *p;
434
435 printf("Testing DRAM from 0x%08x to 0x%08x\n",
436 CFG_MEMTEST_START,
437 CFG_MEMTEST_END);
438
439 printf("DRAM test phase 1:\n");
440 for (p = pstart; p < pend; p++)
441 *p = 0xaaaaaaaa;
442
443 for (p = pstart; p < pend; p++) {
444 if (*p != 0xaaaaaaaa) {
445 printf ("DRAM test fails at: %08x\n", (uint) p);
446 return 1;
447 }
448 }
449
450 printf("DRAM test phase 2:\n");
451 for (p = pstart; p < pend; p++)
452 *p = 0x55555555;
453
454 for (p = pstart; p < pend; p++) {
455 if (*p != 0x55555555) {
456 printf ("DRAM test fails at: %08x\n", (uint) p);
457 return 1;
458 }
459 }
460
461 printf("DRAM test passed.\n");
462 return 0;
463}
464#endif
465
Matthew McClintock3b662012006-06-28 10:46:13 -0500466#ifdef CONFIG_PCI
467/* For some reason the Tundra PCI bridge shows up on itself as a
468 * different device. Work around that by refusing to configure it
wdenk0aeb8532004-10-10 21:21:55 +0000469 */
Matthew McClintock3b662012006-06-28 10:46:13 -0500470void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
wdenk0aeb8532004-10-10 21:21:55 +0000471
wdenk0aeb8532004-10-10 21:21:55 +0000472static struct pci_config_table pci_mpc85xxcds_config_table[] = {
Matthew McClintock3b662012006-06-28 10:46:13 -0500473 {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700474 {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
475 {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
Andy Flemingdcd580b2007-02-24 01:08:13 -0600476 mpc85xx_config_via_usbide, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700477 {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
478 mpc85xx_config_via_usb, {0,0,0}},
479 {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
480 mpc85xx_config_via_usb2, {0,0,0}},
481 {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
Andy Flemingdcd580b2007-02-24 01:08:13 -0600482 mpc85xx_config_via_power, {0,0,0}},
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700483 {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
484 mpc85xx_config_via_ac97, {0,0,0}},
Andy Flemingdcd580b2007-02-24 01:08:13 -0600485 {},
wdenk0aeb8532004-10-10 21:21:55 +0000486};
wdenk0aeb8532004-10-10 21:21:55 +0000487
Matthew McClintock3b662012006-06-28 10:46:13 -0500488
489static struct pci_controller hose[] = {
490 {
wdenk0aeb8532004-10-10 21:21:55 +0000491 config_table: pci_mpc85xxcds_config_table,
Matthew McClintock3b662012006-06-28 10:46:13 -0500492 },
493#ifdef CONFIG_MPC85XX_PCI2
Andy Flemingdcd580b2007-02-24 01:08:13 -0600494 {},
wdenk0aeb8532004-10-10 21:21:55 +0000495#endif
496};
497
Matthew McClintock3b662012006-06-28 10:46:13 -0500498#endif
wdenk0aeb8532004-10-10 21:21:55 +0000499
wdenk0aeb8532004-10-10 21:21:55 +0000500void
501pci_init_board(void)
502{
503#ifdef CONFIG_PCI
Matthew McClintockf32ef672006-06-28 10:46:35 -0500504 pci_mpc85xx_init(hose);
wdenk0aeb8532004-10-10 21:21:55 +0000505#endif
506}