Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2016 Google, Inc |
| 4 | * (C) Copyright 2008-2014 Rockchip Electronics |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_PWM_H |
| 8 | #define _ASM_ARCH_PWM_H |
| 9 | |
David Wu | eb82918 | 2019-12-03 17:49:53 +0800 | [diff] [blame^] | 10 | struct rockchip_pwm_regs { |
| 11 | unsigned long duty; |
| 12 | unsigned long period; |
| 13 | unsigned long cntr; |
| 14 | unsigned long ctrl; |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 15 | }; |
David Wu | eb82918 | 2019-12-03 17:49:53 +0800 | [diff] [blame^] | 16 | |
| 17 | #define PWM_CTRL_TIMER_EN (1 << 0) |
| 18 | #define PWM_CTRL_OUTPUT_EN (1 << 3) |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 19 | |
| 20 | #define RK_PWM_DISABLE (0 << 0) |
| 21 | #define RK_PWM_ENABLE (1 << 0) |
| 22 | |
| 23 | #define PWM_ONE_SHOT (0 << 1) |
| 24 | #define PWM_CONTINUOUS (1 << 1) |
| 25 | #define RK_PWM_CAPTURE (1 << 2) |
| 26 | |
| 27 | #define PWM_DUTY_POSTIVE (1 << 3) |
| 28 | #define PWM_DUTY_NEGATIVE (0 << 3) |
Kever Yang | 2291e49 | 2017-07-19 19:54:23 +0800 | [diff] [blame] | 29 | #define PWM_DUTY_MASK (1 << 3) |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 30 | |
| 31 | #define PWM_INACTIVE_POSTIVE (1 << 4) |
| 32 | #define PWM_INACTIVE_NEGATIVE (0 << 4) |
Kever Yang | 2291e49 | 2017-07-19 19:54:23 +0800 | [diff] [blame] | 33 | #define PWM_INACTIVE_MASK (1 << 4) |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 34 | |
| 35 | #define PWM_OUTPUT_LEFT (0 << 5) |
| 36 | #define PWM_OUTPUT_CENTER (1 << 5) |
| 37 | |
David Wu | eb82918 | 2019-12-03 17:49:53 +0800 | [diff] [blame^] | 38 | #define PWM_LOCK (1 << 6) |
| 39 | #define PWM_UNLOCK (0 << 6) |
| 40 | |
Simon Glass | c5915f7 | 2016-01-21 19:44:55 -0700 | [diff] [blame] | 41 | #define PWM_LP_ENABLE (1 << 8) |
| 42 | #define PWM_LP_DISABLE (0 << 8) |
| 43 | |
| 44 | #define PWM_SEL_SCALE_CLK (1 << 9) |
| 45 | #define PWM_SEL_SRC_CLK (0 << 9) |
| 46 | |
| 47 | #endif |