Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2011, Marvell Semiconductor Inc. |
| 4 | * Lei Wen <leiwen@marvell.com> |
| 5 | * |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 6 | * Back ported to the 8xx platform (from the 8260 platform) by |
| 7 | * Murray.Jensen@cmst.csiro.au, 27-Jan-01. |
| 8 | */ |
| 9 | #ifndef __SDHCI_HW_H |
| 10 | #define __SDHCI_HW_H |
| 11 | |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 12 | #include <linux/bitops.h> |
Masahiro Yamada | 32d1213 | 2020-02-14 16:40:22 +0900 | [diff] [blame] | 13 | #include <linux/types.h> |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 14 | #include <asm/io.h> |
Lei Wen | 5a1108e | 2011-10-08 04:14:56 +0000 | [diff] [blame] | 15 | #include <mmc.h> |
Simon Glass | a30d4ba | 2015-01-05 20:05:38 -0700 | [diff] [blame] | 16 | #include <asm/gpio.h> |
Lei Wen | 5a1108e | 2011-10-08 04:14:56 +0000 | [diff] [blame] | 17 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 18 | /* |
| 19 | * Controller registers |
| 20 | */ |
| 21 | |
| 22 | #define SDHCI_DMA_ADDRESS 0x00 |
| 23 | |
| 24 | #define SDHCI_BLOCK_SIZE 0x04 |
| 25 | #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) |
| 26 | |
| 27 | #define SDHCI_BLOCK_COUNT 0x06 |
| 28 | |
| 29 | #define SDHCI_ARGUMENT 0x08 |
| 30 | |
| 31 | #define SDHCI_TRANSFER_MODE 0x0C |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 32 | #define SDHCI_TRNS_DMA BIT(0) |
| 33 | #define SDHCI_TRNS_BLK_CNT_EN BIT(1) |
| 34 | #define SDHCI_TRNS_ACMD12 BIT(2) |
| 35 | #define SDHCI_TRNS_READ BIT(4) |
| 36 | #define SDHCI_TRNS_MULTI BIT(5) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 37 | |
| 38 | #define SDHCI_COMMAND 0x0E |
| 39 | #define SDHCI_CMD_RESP_MASK 0x03 |
| 40 | #define SDHCI_CMD_CRC 0x08 |
| 41 | #define SDHCI_CMD_INDEX 0x10 |
| 42 | #define SDHCI_CMD_DATA 0x20 |
| 43 | #define SDHCI_CMD_ABORTCMD 0xC0 |
| 44 | |
| 45 | #define SDHCI_CMD_RESP_NONE 0x00 |
| 46 | #define SDHCI_CMD_RESP_LONG 0x01 |
| 47 | #define SDHCI_CMD_RESP_SHORT 0x02 |
| 48 | #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 |
| 49 | |
| 50 | #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) |
| 51 | #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f) |
| 52 | |
| 53 | #define SDHCI_RESPONSE 0x10 |
| 54 | |
| 55 | #define SDHCI_BUFFER 0x20 |
| 56 | |
| 57 | #define SDHCI_PRESENT_STATE 0x24 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 58 | #define SDHCI_CMD_INHIBIT BIT(0) |
| 59 | #define SDHCI_DATA_INHIBIT BIT(1) |
| 60 | #define SDHCI_DOING_WRITE BIT(8) |
| 61 | #define SDHCI_DOING_READ BIT(9) |
| 62 | #define SDHCI_SPACE_AVAILABLE BIT(10) |
| 63 | #define SDHCI_DATA_AVAILABLE BIT(11) |
| 64 | #define SDHCI_CARD_PRESENT BIT(16) |
| 65 | #define SDHCI_CARD_STATE_STABLE BIT(17) |
| 66 | #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18) |
| 67 | #define SDHCI_WRITE_PROTECT BIT(19) |
Stephen Carlson | 8cd3128 | 2021-08-17 12:46:41 -0700 | [diff] [blame] | 68 | #define SDHCI_DATA_LVL_MASK 0x00F00000 |
| 69 | #define SDHCI_DATA_0_LVL_MASK BIT(20) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 70 | |
| 71 | #define SDHCI_HOST_CONTROL 0x28 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 72 | #define SDHCI_CTRL_LED BIT(0) |
| 73 | #define SDHCI_CTRL_4BITBUS BIT(1) |
| 74 | #define SDHCI_CTRL_HISPD BIT(2) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 75 | #define SDHCI_CTRL_DMA_MASK 0x18 |
| 76 | #define SDHCI_CTRL_SDMA 0x00 |
| 77 | #define SDHCI_CTRL_ADMA1 0x08 |
| 78 | #define SDHCI_CTRL_ADMA32 0x10 |
| 79 | #define SDHCI_CTRL_ADMA64 0x18 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 80 | #define SDHCI_CTRL_8BITBUS BIT(5) |
| 81 | #define SDHCI_CTRL_CD_TEST_INS BIT(6) |
| 82 | #define SDHCI_CTRL_CD_TEST BIT(7) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 83 | |
| 84 | #define SDHCI_POWER_CONTROL 0x29 |
| 85 | #define SDHCI_POWER_ON 0x01 |
| 86 | #define SDHCI_POWER_180 0x0A |
| 87 | #define SDHCI_POWER_300 0x0C |
| 88 | #define SDHCI_POWER_330 0x0E |
| 89 | |
| 90 | #define SDHCI_BLOCK_GAP_CONTROL 0x2A |
| 91 | |
| 92 | #define SDHCI_WAKE_UP_CONTROL 0x2B |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 93 | #define SDHCI_WAKE_ON_INT BIT(0) |
| 94 | #define SDHCI_WAKE_ON_INSERT BIT(1) |
| 95 | #define SDHCI_WAKE_ON_REMOVE BIT(2) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 96 | |
| 97 | #define SDHCI_CLOCK_CONTROL 0x2C |
| 98 | #define SDHCI_DIVIDER_SHIFT 8 |
| 99 | #define SDHCI_DIVIDER_HI_SHIFT 6 |
| 100 | #define SDHCI_DIV_MASK 0xFF |
| 101 | #define SDHCI_DIV_MASK_LEN 8 |
| 102 | #define SDHCI_DIV_HI_MASK 0x300 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 103 | #define SDHCI_PROG_CLOCK_MODE BIT(5) |
| 104 | #define SDHCI_CLOCK_CARD_EN BIT(2) |
| 105 | #define SDHCI_CLOCK_INT_STABLE BIT(1) |
| 106 | #define SDHCI_CLOCK_INT_EN BIT(0) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 107 | |
| 108 | #define SDHCI_TIMEOUT_CONTROL 0x2E |
| 109 | |
| 110 | #define SDHCI_SOFTWARE_RESET 0x2F |
| 111 | #define SDHCI_RESET_ALL 0x01 |
| 112 | #define SDHCI_RESET_CMD 0x02 |
| 113 | #define SDHCI_RESET_DATA 0x04 |
| 114 | |
| 115 | #define SDHCI_INT_STATUS 0x30 |
| 116 | #define SDHCI_INT_ENABLE 0x34 |
| 117 | #define SDHCI_SIGNAL_ENABLE 0x38 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 118 | #define SDHCI_INT_RESPONSE BIT(0) |
| 119 | #define SDHCI_INT_DATA_END BIT(1) |
| 120 | #define SDHCI_INT_DMA_END BIT(3) |
| 121 | #define SDHCI_INT_SPACE_AVAIL BIT(4) |
| 122 | #define SDHCI_INT_DATA_AVAIL BIT(5) |
| 123 | #define SDHCI_INT_CARD_INSERT BIT(6) |
| 124 | #define SDHCI_INT_CARD_REMOVE BIT(7) |
| 125 | #define SDHCI_INT_CARD_INT BIT(8) |
| 126 | #define SDHCI_INT_ERROR BIT(15) |
| 127 | #define SDHCI_INT_TIMEOUT BIT(16) |
| 128 | #define SDHCI_INT_CRC BIT(17) |
| 129 | #define SDHCI_INT_END_BIT BIT(18) |
| 130 | #define SDHCI_INT_INDEX BIT(19) |
| 131 | #define SDHCI_INT_DATA_TIMEOUT BIT(20) |
| 132 | #define SDHCI_INT_DATA_CRC BIT(21) |
| 133 | #define SDHCI_INT_DATA_END_BIT BIT(22) |
| 134 | #define SDHCI_INT_BUS_POWER BIT(23) |
| 135 | #define SDHCI_INT_ACMD12ERR BIT(24) |
| 136 | #define SDHCI_INT_ADMA_ERROR BIT(25) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 137 | |
| 138 | #define SDHCI_INT_NORMAL_MASK 0x00007FFF |
| 139 | #define SDHCI_INT_ERROR_MASK 0xFFFF8000 |
| 140 | |
| 141 | #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ |
| 142 | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) |
| 143 | #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ |
| 144 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ |
| 145 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ |
| 146 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR) |
| 147 | #define SDHCI_INT_ALL_MASK ((unsigned int)-1) |
| 148 | |
| 149 | #define SDHCI_ACMD12_ERR 0x3C |
| 150 | |
Faiz Abbas | 2eddc00 | 2019-06-11 00:43:40 +0530 | [diff] [blame] | 151 | #define SDHCI_HOST_CONTROL2 0x3E |
| 152 | #define SDHCI_CTRL_UHS_MASK 0x0007 |
| 153 | #define SDHCI_CTRL_UHS_SDR12 0x0000 |
| 154 | #define SDHCI_CTRL_UHS_SDR25 0x0001 |
| 155 | #define SDHCI_CTRL_UHS_SDR50 0x0002 |
| 156 | #define SDHCI_CTRL_UHS_SDR104 0x0003 |
| 157 | #define SDHCI_CTRL_UHS_DDR50 0x0004 |
| 158 | #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ |
| 159 | #define SDHCI_CTRL_VDD_180 0x0008 |
| 160 | #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 |
| 161 | #define SDHCI_CTRL_DRV_TYPE_B 0x0000 |
| 162 | #define SDHCI_CTRL_DRV_TYPE_A 0x0010 |
| 163 | #define SDHCI_CTRL_DRV_TYPE_C 0x0020 |
| 164 | #define SDHCI_CTRL_DRV_TYPE_D 0x0030 |
| 165 | #define SDHCI_CTRL_EXEC_TUNING 0x0040 |
| 166 | #define SDHCI_CTRL_TUNED_CLK 0x0080 |
| 167 | #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 168 | |
| 169 | #define SDHCI_CAPABILITIES 0x40 |
| 170 | #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F |
| 171 | #define SDHCI_TIMEOUT_CLK_SHIFT 0 |
| 172 | #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 |
| 173 | #define SDHCI_CLOCK_BASE_MASK 0x00003F00 |
| 174 | #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 |
| 175 | #define SDHCI_CLOCK_BASE_SHIFT 8 |
| 176 | #define SDHCI_MAX_BLOCK_MASK 0x00030000 |
| 177 | #define SDHCI_MAX_BLOCK_SHIFT 16 |
Jaehoon Chung | 07d012c | 2016-12-30 15:30:19 +0900 | [diff] [blame] | 178 | #define SDHCI_CAN_DO_8BIT BIT(18) |
| 179 | #define SDHCI_CAN_DO_ADMA2 BIT(19) |
| 180 | #define SDHCI_CAN_DO_ADMA1 BIT(20) |
| 181 | #define SDHCI_CAN_DO_HISPD BIT(21) |
| 182 | #define SDHCI_CAN_DO_SDMA BIT(22) |
| 183 | #define SDHCI_CAN_VDD_330 BIT(24) |
| 184 | #define SDHCI_CAN_VDD_300 BIT(25) |
| 185 | #define SDHCI_CAN_VDD_180 BIT(26) |
| 186 | #define SDHCI_CAN_64BIT BIT(28) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 187 | |
| 188 | #define SDHCI_CAPABILITIES_1 0x44 |
Siva Durga Prasad Paladugu | c0290b4 | 2018-04-19 12:37:08 +0530 | [diff] [blame] | 189 | #define SDHCI_SUPPORT_SDR50 0x00000001 |
| 190 | #define SDHCI_SUPPORT_SDR104 0x00000002 |
| 191 | #define SDHCI_SUPPORT_DDR50 0x00000004 |
| 192 | #define SDHCI_USE_SDR50_TUNING 0x00002000 |
| 193 | |
Wenyou Yang | 83e88a4 | 2016-08-10 10:51:05 +0800 | [diff] [blame] | 194 | #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 |
| 195 | #define SDHCI_CLOCK_MUL_SHIFT 16 |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 196 | |
| 197 | #define SDHCI_MAX_CURRENT 0x48 |
| 198 | |
| 199 | /* 4C-4F reserved for more max current */ |
| 200 | |
| 201 | #define SDHCI_SET_ACMD12_ERROR 0x50 |
| 202 | #define SDHCI_SET_INT_ERROR 0x52 |
| 203 | |
| 204 | #define SDHCI_ADMA_ERROR 0x54 |
| 205 | |
| 206 | /* 55-57 reserved */ |
| 207 | |
| 208 | #define SDHCI_ADMA_ADDRESS 0x58 |
Faiz Abbas | 4c082a6 | 2019-04-16 23:06:58 +0530 | [diff] [blame] | 209 | #define SDHCI_ADMA_ADDRESS_HI 0x5c |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 210 | |
| 211 | /* 60-FB reserved */ |
| 212 | |
| 213 | #define SDHCI_SLOT_INT_STATUS 0xFC |
| 214 | |
| 215 | #define SDHCI_HOST_VERSION 0xFE |
| 216 | #define SDHCI_VENDOR_VER_MASK 0xFF00 |
| 217 | #define SDHCI_VENDOR_VER_SHIFT 8 |
| 218 | #define SDHCI_SPEC_VER_MASK 0x00FF |
| 219 | #define SDHCI_SPEC_VER_SHIFT 0 |
| 220 | #define SDHCI_SPEC_100 0 |
| 221 | #define SDHCI_SPEC_200 1 |
| 222 | #define SDHCI_SPEC_300 2 |
| 223 | |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 224 | #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK) |
| 225 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 226 | /* |
| 227 | * End of controller registers. |
| 228 | */ |
| 229 | |
| 230 | #define SDHCI_MAX_DIV_SPEC_200 256 |
| 231 | #define SDHCI_MAX_DIV_SPEC_300 2046 |
| 232 | |
| 233 | /* |
| 234 | * quirks |
| 235 | */ |
| 236 | #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) |
Ajay Bhargav | dab5d4d | 2011-11-13 23:43:12 +0000 | [diff] [blame] | 237 | #define SDHCI_QUIRK_REG32_RW (1 << 1) |
Jaehoon Chung | 89237a8 | 2012-04-23 02:36:25 +0000 | [diff] [blame] | 238 | #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 239 | #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) |
| 240 | #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) |
Hannes Schmelzer | 576a018 | 2018-03-07 08:00:56 +0100 | [diff] [blame] | 241 | /* |
| 242 | * SDHCI_QUIRK_BROKEN_HISPD_MODE |
| 243 | * the hardware cannot operate correctly in high-speed mode, |
| 244 | * this quirk forces the sdhci host-controller to non high-speed mode |
| 245 | */ |
| 246 | #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5) |
Tushar Behera | 0fba4c2 | 2012-09-20 20:31:57 +0000 | [diff] [blame] | 247 | #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) |
Jaehoon Chung | 46e627c | 2013-07-19 17:44:49 +0900 | [diff] [blame] | 248 | #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) |
Ashok Reddy Soma | 61e0df9 | 2020-10-23 04:58:57 -0600 | [diff] [blame] | 249 | #define SDHCI_QUIRK_NO_1_8_V (1 << 9) |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 250 | |
Lei Wen | dd1298c | 2011-10-08 04:14:55 +0000 | [diff] [blame] | 251 | /* to make gcc happy */ |
| 252 | struct sdhci_host; |
| 253 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 254 | /* |
| 255 | * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. |
| 256 | */ |
| 257 | #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) |
| 258 | #define SDHCI_DEFAULT_BOUNDARY_ARG (7) |
| 259 | struct sdhci_ops { |
| 260 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
Jaehoon Chung | 46d3c03 | 2016-12-30 15:30:18 +0900 | [diff] [blame] | 261 | u32 (*read_l)(struct sdhci_host *host, int reg); |
| 262 | u16 (*read_w)(struct sdhci_host *host, int reg); |
| 263 | u8 (*read_b)(struct sdhci_host *host, int reg); |
| 264 | void (*write_l)(struct sdhci_host *host, u32 val, int reg); |
| 265 | void (*write_w)(struct sdhci_host *host, u16 val, int reg); |
| 266 | void (*write_b)(struct sdhci_host *host, u8 val, int reg); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 267 | #endif |
Jaehoon Chung | 46d3c03 | 2016-12-30 15:30:18 +0900 | [diff] [blame] | 268 | int (*get_cd)(struct sdhci_host *host); |
| 269 | void (*set_control_reg)(struct sdhci_host *host); |
Faiz Abbas | 375acf8 | 2019-06-11 00:43:37 +0530 | [diff] [blame] | 270 | int (*set_ios_post)(struct sdhci_host *host); |
Jaehoon Chung | 46d3c03 | 2016-12-30 15:30:18 +0900 | [diff] [blame] | 271 | void (*set_clock)(struct sdhci_host *host, u32 div); |
Siva Durga Prasad Paladugu | 9f044d4 | 2018-04-19 12:37:06 +0530 | [diff] [blame] | 272 | int (*platform_execute_tuning)(struct mmc *host, u8 opcode); |
Ashok Reddy Soma | 6b67778 | 2021-08-02 23:20:41 -0600 | [diff] [blame] | 273 | int (*set_delay)(struct sdhci_host *host); |
Faiz Abbas | d222921 | 2020-02-26 13:44:31 +0530 | [diff] [blame] | 274 | int (*deferred_probe)(struct sdhci_host *host); |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 275 | }; |
| 276 | |
Faiz Abbas | 4c082a6 | 2019-04-16 23:06:58 +0530 | [diff] [blame] | 277 | #define ADMA_MAX_LEN 65532 |
| 278 | #ifdef CONFIG_DMA_ADDR_T_64BIT |
| 279 | #define ADMA_DESC_LEN 16 |
| 280 | #else |
| 281 | #define ADMA_DESC_LEN 8 |
| 282 | #endif |
| 283 | #define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \ |
| 284 | MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN |
| 285 | |
| 286 | #define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN) |
| 287 | |
| 288 | /* Decriptor table defines */ |
| 289 | #define ADMA_DESC_ATTR_VALID BIT(0) |
| 290 | #define ADMA_DESC_ATTR_END BIT(1) |
| 291 | #define ADMA_DESC_ATTR_INT BIT(2) |
| 292 | #define ADMA_DESC_ATTR_ACT1 BIT(4) |
| 293 | #define ADMA_DESC_ATTR_ACT2 BIT(5) |
| 294 | |
| 295 | #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 |
| 296 | #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) |
| 297 | |
| 298 | struct sdhci_adma_desc { |
| 299 | u8 attr; |
| 300 | u8 reserved; |
| 301 | u16 len; |
| 302 | u32 addr_lo; |
| 303 | #ifdef CONFIG_DMA_ADDR_T_64BIT |
| 304 | u32 addr_hi; |
| 305 | #endif |
| 306 | } __packed; |
Michael Walle | 02016c6 | 2020-09-23 12:42:51 +0200 | [diff] [blame] | 307 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 308 | struct sdhci_host { |
Masahiro Yamada | a440561 | 2016-04-22 20:59:31 +0900 | [diff] [blame] | 309 | const char *name; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 310 | void *ioaddr; |
| 311 | unsigned int quirks; |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 312 | unsigned int host_caps; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 313 | unsigned int version; |
Stefan Herbrechtsmeier | bc47e0e | 2017-01-17 15:58:48 +0100 | [diff] [blame] | 314 | unsigned int max_clk; /* Maximum Base Clock frequency */ |
Wenyou Yang | 3d73404 | 2016-09-18 09:01:22 +0800 | [diff] [blame] | 315 | unsigned int clk_mul; /* Clock Multiplier value */ |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 316 | unsigned int clock; |
Lei Wen | 5a1108e | 2011-10-08 04:14:56 +0000 | [diff] [blame] | 317 | struct mmc *mmc; |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 318 | const struct sdhci_ops *ops; |
Jaehoon Chung | b1929ea | 2012-08-30 16:24:11 +0000 | [diff] [blame] | 319 | int index; |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 320 | |
Piotr Wilczek | 12cf19e | 2014-03-07 14:59:41 +0100 | [diff] [blame] | 321 | int bus_width; |
Simon Glass | a30d4ba | 2015-01-05 20:05:38 -0700 | [diff] [blame] | 322 | struct gpio_desc pwr_gpio; /* Power GPIO */ |
| 323 | struct gpio_desc cd_gpio; /* Card Detect GPIO */ |
Piotr Wilczek | 12cf19e | 2014-03-07 14:59:41 +0100 | [diff] [blame] | 324 | |
Jaehoon Chung | 53889ed | 2012-04-23 02:36:26 +0000 | [diff] [blame] | 325 | uint voltages; |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 326 | |
| 327 | struct mmc_config cfg; |
Masahiro Yamada | c3a17af | 2020-02-14 16:40:21 +0900 | [diff] [blame] | 328 | void *align_buffer; |
Masahiro Yamada | 32d1213 | 2020-02-14 16:40:22 +0900 | [diff] [blame] | 329 | bool force_align_buffer; |
Faiz Abbas | 8710250 | 2019-04-16 23:06:57 +0530 | [diff] [blame] | 330 | dma_addr_t start_addr; |
| 331 | int flags; |
| 332 | #define USE_SDMA (0x1 << 0) |
Faiz Abbas | 4c082a6 | 2019-04-16 23:06:58 +0530 | [diff] [blame] | 333 | #define USE_ADMA (0x1 << 1) |
| 334 | #define USE_ADMA64 (0x1 << 2) |
| 335 | #define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64) |
| 336 | dma_addr_t adma_addr; |
| 337 | #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) |
| 338 | struct sdhci_adma_desc *adma_desc_table; |
Faiz Abbas | 4c082a6 | 2019-04-16 23:06:58 +0530 | [diff] [blame] | 339 | #endif |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 340 | }; |
| 341 | |
| 342 | #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS |
| 343 | |
| 344 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 345 | { |
| 346 | if (unlikely(host->ops->write_l)) |
| 347 | host->ops->write_l(host, val, reg); |
| 348 | else |
| 349 | writel(val, host->ioaddr + reg); |
| 350 | } |
| 351 | |
| 352 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 353 | { |
| 354 | if (unlikely(host->ops->write_w)) |
| 355 | host->ops->write_w(host, val, reg); |
| 356 | else |
| 357 | writew(val, host->ioaddr + reg); |
| 358 | } |
| 359 | |
| 360 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 361 | { |
| 362 | if (unlikely(host->ops->write_b)) |
| 363 | host->ops->write_b(host, val, reg); |
| 364 | else |
| 365 | writeb(val, host->ioaddr + reg); |
| 366 | } |
| 367 | |
| 368 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 369 | { |
| 370 | if (unlikely(host->ops->read_l)) |
| 371 | return host->ops->read_l(host, reg); |
| 372 | else |
| 373 | return readl(host->ioaddr + reg); |
| 374 | } |
| 375 | |
| 376 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 377 | { |
| 378 | if (unlikely(host->ops->read_w)) |
| 379 | return host->ops->read_w(host, reg); |
| 380 | else |
| 381 | return readw(host->ioaddr + reg); |
| 382 | } |
| 383 | |
| 384 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 385 | { |
| 386 | if (unlikely(host->ops->read_b)) |
| 387 | return host->ops->read_b(host, reg); |
| 388 | else |
| 389 | return readb(host->ioaddr + reg); |
| 390 | } |
| 391 | |
| 392 | #else |
| 393 | |
| 394 | static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) |
| 395 | { |
| 396 | writel(val, host->ioaddr + reg); |
| 397 | } |
| 398 | |
| 399 | static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) |
| 400 | { |
| 401 | writew(val, host->ioaddr + reg); |
| 402 | } |
| 403 | |
| 404 | static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) |
| 405 | { |
| 406 | writeb(val, host->ioaddr + reg); |
| 407 | } |
| 408 | static inline u32 sdhci_readl(struct sdhci_host *host, int reg) |
| 409 | { |
| 410 | return readl(host->ioaddr + reg); |
| 411 | } |
| 412 | |
| 413 | static inline u16 sdhci_readw(struct sdhci_host *host, int reg) |
| 414 | { |
| 415 | return readw(host->ioaddr + reg); |
| 416 | } |
| 417 | |
| 418 | static inline u8 sdhci_readb(struct sdhci_host *host, int reg) |
| 419 | { |
| 420 | return readb(host->ioaddr + reg); |
| 421 | } |
| 422 | #endif |
| 423 | |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 424 | #ifdef CONFIG_BLK |
| 425 | /** |
| 426 | * sdhci_setup_cfg() - Set up the configuration for DWMMC |
| 427 | * |
| 428 | * This is used to set up an SDHCI device when you are using CONFIG_BLK. |
| 429 | * |
| 430 | * This should be called from your MMC driver's probe() method once you have |
| 431 | * the information required. |
| 432 | * |
| 433 | * Generally your driver will have a platform data structure which holds both |
| 434 | * the configuration (struct mmc_config) and the MMC device info (struct mmc). |
| 435 | * For example: |
| 436 | * |
| 437 | * struct msm_sdhc_plat { |
| 438 | * struct mmc_config cfg; |
| 439 | * struct mmc mmc; |
| 440 | * }; |
| 441 | * |
| 442 | * ... |
| 443 | * |
| 444 | * Inside U_BOOT_DRIVER(): |
Simon Glass | 71fa5b4 | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 445 | * .plat_auto = sizeof(struct msm_sdhc_plat), |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 446 | * |
| 447 | * To access platform data: |
Simon Glass | fa20e93 | 2020-12-03 16:55:20 -0700 | [diff] [blame] | 448 | * struct msm_sdhc_plat *plat = dev_get_plat(dev); |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 449 | * |
| 450 | * See msm_sdhci.c for an example. |
| 451 | * |
| 452 | * @cfg: Configuration structure to fill in (generally &plat->mmc) |
Jaehoon Chung | 8a5ffbb | 2016-07-26 19:06:24 +0900 | [diff] [blame] | 453 | * @host: SDHCI host structure |
Stefan Herbrechtsmeier | bc47e0e | 2017-01-17 15:58:48 +0100 | [diff] [blame] | 454 | * @f_max: Maximum supported clock frequency in HZ (0 for default) |
| 455 | * @f_min: Minimum supported clock frequency in HZ (0 for default) |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 456 | */ |
Jaehoon Chung | 8a5ffbb | 2016-07-26 19:06:24 +0900 | [diff] [blame] | 457 | int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, |
Stefan Herbrechtsmeier | bc47e0e | 2017-01-17 15:58:48 +0100 | [diff] [blame] | 458 | u32 f_max, u32 f_min); |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 459 | |
| 460 | /** |
| 461 | * sdhci_bind() - Set up a new MMC block device |
| 462 | * |
| 463 | * This is used to set up an SDHCI block device when you are using CONFIG_BLK. |
| 464 | * It should be called from your driver's bind() method. |
| 465 | * |
| 466 | * See msm_sdhci.c for an example. |
| 467 | * |
| 468 | * @dev: Device to set up |
| 469 | * @mmc: Pointer to mmc structure (normally &plat->mmc) |
| 470 | * @cfg: Empty configuration structure (generally &plat->cfg). This is |
| 471 | * normally all zeroes at this point. The only purpose of passing |
| 472 | * this in is to set mmc->cfg to it. |
| 473 | * @return 0 if OK, -ve if the block device could not be created |
| 474 | */ |
| 475 | int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg); |
| 476 | #else |
| 477 | |
| 478 | /** |
| 479 | * add_sdhci() - Add a new SDHCI interface |
| 480 | * |
| 481 | * This is used when you are not using CONFIG_BLK. Convert your driver over! |
| 482 | * |
| 483 | * @host: SDHCI host structure |
Stefan Herbrechtsmeier | bc47e0e | 2017-01-17 15:58:48 +0100 | [diff] [blame] | 484 | * @f_max: Maximum supported clock frequency in HZ (0 for default) |
| 485 | * @f_min: Minimum supported clock frequency in HZ (0 for default) |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 486 | * @return 0 if OK, -ve on error |
| 487 | */ |
Stefan Herbrechtsmeier | bc47e0e | 2017-01-17 15:58:48 +0100 | [diff] [blame] | 488 | int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min); |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 489 | #endif /* !CONFIG_BLK */ |
| 490 | |
Faiz Abbas | 2eddc00 | 2019-06-11 00:43:40 +0530 | [diff] [blame] | 491 | void sdhci_set_uhs_timing(struct sdhci_host *host); |
Simon Glass | eba48f9 | 2017-07-29 11:35:31 -0600 | [diff] [blame] | 492 | #ifdef CONFIG_DM_MMC |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 493 | /* Export the operations to drivers */ |
| 494 | int sdhci_probe(struct udevice *dev); |
Faiz Abbas | ab61966 | 2019-06-11 00:43:35 +0530 | [diff] [blame] | 495 | int sdhci_set_clock(struct mmc *mmc, unsigned int clock); |
Faiz Abbas | 6ede121 | 2021-02-04 15:10:46 +0530 | [diff] [blame] | 496 | |
| 497 | /** |
| 498 | * sdhci_set_control_reg - Set control registers |
| 499 | * |
| 500 | * This is used set up control registers for voltage level and UHS speed |
| 501 | * mode. |
| 502 | * |
| 503 | * @host: SDHCI host structure |
| 504 | */ |
| 505 | void sdhci_set_control_reg(struct sdhci_host *host); |
Simon Glass | b97f0fa | 2016-06-12 23:30:28 -0600 | [diff] [blame] | 506 | extern const struct dm_mmc_ops sdhci_ops; |
| 507 | #else |
| 508 | #endif |
| 509 | |
Michael Walle | 02016c6 | 2020-09-23 12:42:51 +0200 | [diff] [blame] | 510 | struct sdhci_adma_desc *sdhci_adma_init(void); |
| 511 | void sdhci_prepare_adma_table(struct sdhci_adma_desc *table, |
| 512 | struct mmc_data *data, dma_addr_t addr); |
| 513 | |
Lei Wen | 142c8f9 | 2011-06-28 21:50:06 +0000 | [diff] [blame] | 514 | #endif /* __SDHCI_HW_H */ |