Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / eb59024f7078c615dea2ed79e93dc577f42fc6eb / . / arch / mips / cpu / mips64 / start.S
blob: 80e6bb1398db3690c5398e50edc2dbee20a861c4 [file] [log] [blame]
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]1/*
2 * Startup Code for MIPS64 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any dlater version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <asm-offsets.h>
26#include <config.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29
30#ifndef CONFIG_SYS_MIPS_CACHE_MODE
31#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
32#endif
33
34 /*
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
37 * 64-bit addresses.
38 */
39 .macro setup_c0_status set clr
40 .set push
41 mfc0 t0, CP0_STATUS
42 or t0, ST0_CU0 | \set | 0x1f | \clr
43 xor t0, 0x1f | \clr
44 mtc0 t0, CP0_STATUS
45 .set noreorder
46 sll zero, 3 # ehb
47 .set pop
48 .endm
49
50 .set noreorder
51
52 .globl _start
53 .text
54_start:
55 .org 0x000
56 b reset
57 nop
58 .org 0x080
59 b romReserved
60 nop
61 .org 0x100
62 b romReserved
63 nop
64 .org 0x180
65 b romReserved
66 nop
67 .org 0x200
68 b romReserved
69 nop
70 .org 0x280
71 b romReserved
72 nop
73 .org 0x300
74 b romReserved
75 nop
76 .org 0x380
77 b romReserved
78 nop
79 .org 0x480
80 b romReserved
81 nop
82
83 /*
84 * We hope there are no more reserved vectors!
85 * 128 * 8 == 1024 == 0x400
86 * so this is address R_VEC+0x400 == 0xbfc00400
87 */
88 .org 0x500
89 .align 4
90reset:
91
92 /* Clear watch registers */
93 dmtc0 zero, CP0_WATCHLO
94 dmtc0 zero, CP0_WATCHHI
95
96 /* WP(Watch Pending), SW0/1 should be cleared */
97 mtc0 zero, CP0_CAUSE
98
99 setup_c0_status ST0_KX 0
100
101 /* Init Timer */
102 mtc0 zero, CP0_COUNT
103 mtc0 zero, CP0_COMPARE
104
105#ifndef CONFIG_SKIP_LOWLEVEL_INIT
106 /* CONFIG0 register */
107 dli t0, CONF_CM_UNCACHED
108 mtc0 t0, CP0_CONFIG
109#endif
110
Zhi-zhou Zhang26dd82b2012-11-24 05:07:12 +0000[diff] [blame]111 /*
112 * Initialize $gp, force 8 byte alignment of bal instruction to forbid
113 * the compiler to put nop's between bal and _gp. This is required to
114 * keep _gp and ra aligned to 8 byte.
115 */
116 .align 3
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]117 bal 1f
118 nop
119 .dword _gp
1201:
121 ld gp, 0(ra)
122
123#ifndef CONFIG_SKIP_LOWLEVEL_INIT
124 /* Initialize any external memory */
125 dla t9, lowlevel_init
126 jalr t9
127 nop
128
129 /* Initialize caches... */
130 dla t9, mips_cache_reset
131 jalr t9
132 nop
133
134 /* ... and enable them */
135 dli t0, CONFIG_SYS_MIPS_CACHE_MODE
136 mtc0 t0, CP0_CONFIG
137#endif
138
139 /* Set up temporary stack */
Gabor Juhosd9bcb6c2013-01-24 06:27:52 +0000[diff] [blame]140 dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]141
142 dla t9, board_init_f
143 jr t9
144 nop
145
146/*
147 * void relocate_code (addr_sp, gd, addr_moni)
148 *
149 * This "function" does not return, instead it continues in RAM
150 * after relocating the monitor code.
151 *
152 * a0 = addr_sp
153 * a1 = gd
154 * a2 = destination address
155 */
156 .globl relocate_code
157 .ent relocate_code
158relocate_code:
159 move sp, a0 # set new stack pointer
160
Gabor Juhosf902d462013-01-24 06:27:53 +0000[diff] [blame]161 move s0, a1 # save gd in s0
162 move s2, a2 # save destination address in s2
163
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]164 dli t0, CONFIG_SYS_MONITOR_BASE
Gabor Juhosfac2f652013-01-24 06:27:54 +0000[diff] [blame]165 dsub s1, s2, t0 # s1 <-- relocation offset
166
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]167 dla t3, in_ram
168 ld t2, -24(t3) # t2 <-- uboot_end_data
169 move t1, a2
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]170
Gabor Juhosfac2f652013-01-24 06:27:54 +0000[diff] [blame]171 dadd gp, s1 # adjust gp
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]172
173 /*
174 * t0 = source address
175 * t1 = target address
176 * t2 = source end address
177 */
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]1781:
179 lw t3, 0(t0)
180 sw t3, 0(t1)
181 daddu t0, 4
Gabor Juhos9a081ab2013-01-24 06:27:51 +0000[diff] [blame]182 blt t0, t2, 1b
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]183 daddu t1, 4
184
185 /* If caches were enabled, we would have to flush them here. */
Gabor Juhoseb590242013-01-24 06:27:55 +0000[diff] [blame^]186 dsub a1, t1, s2 # a1 <-- size
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]187 dla t9, flush_cache
188 jalr t9
Gabor Juhoseb590242013-01-24 06:27:55 +0000[diff] [blame^]189 move a0, s2 # a0 <-- destination address
Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame]190
191 /* Jump to where we've relocated ourselves */
192 daddi t0, s2, in_ram - _start
193 jr t0
194 nop
195
196 .dword _gp
197 .dword _GLOBAL_OFFSET_TABLE_
198 .dword uboot_end_data
199 .dword uboot_end
200 .dword num_got_entries
201
202in_ram:
203 /*
204 * Now we want to update GOT.
205 *
206 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
207 * generated by GNU ld. Skip these reserved entries from relocation.
208 */
209 ld t3, -8(t0) # t3 <-- num_got_entries
210 ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
211 ld t9, -40(t0) # t9 <-- _gp
212 dsub t8, t9 # compute offset
213 dadd t8, t8, gp # t8 now holds relocated _G_O_T_
214 daddi t8, t8, 16 # skipping first two entries
215 dli t2, 2
2161:
217 ld t1, 0(t8)
218 beqz t1, 2f
219 dadd t1, s1
220 sd t1, 0(t8)
2212:
222 daddi t2, 1
223 blt t2, t3, 1b
224 daddi t8, 8
225
226 /* Clear BSS */
227 ld t1, -24(t0) # t1 <-- uboot_end_data
228 ld t2, -16(t0) # t2 <-- uboot_end
229 dadd t1, s1 # adjust pointers
230 dadd t2, s1
231
232 dsub t1, 8
2331:
234 daddi t1, 8
235 bltl t1, t2, 1b
236 sd zero, 0(t1)
237
238 move a0, s0 # a0 <-- gd
239 dla t9, board_init_r
240 jr t9
241 move a1, s2
242
243 .end relocate_code
244
245 /* Exception handlers */
246romReserved:
247 b romReserved
Gabor Juhos9d632e62013-01-16 03:05:01 +0000[diff] [blame]248 nop