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git01.mediatek.com / filogic / uboot / e0d6df582d9fda2eb35bd57a343bc24dd9e37b6a / . / arch / mips / cpu / mips64 / start.S
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Zhi-zhou Zhange0d6df52012-10-16 15:02:08 +0200[diff] [blame^]1/*
2 * Startup Code for MIPS64 CPU-core
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any dlater version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <asm-offsets.h>
26#include <config.h>
27#include <asm/regdef.h>
28#include <asm/mipsregs.h>
29
30#ifndef CONFIG_SYS_MIPS_CACHE_MODE
31#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
32#endif
33
34 /*
35 * For the moment disable interrupts, mark the kernel mode and
36 * set ST0_KX so that the CPU does not spit fire when using
37 * 64-bit addresses.
38 */
39 .macro setup_c0_status set clr
40 .set push
41 mfc0 t0, CP0_STATUS
42 or t0, ST0_CU0 | \set | 0x1f | \clr
43 xor t0, 0x1f | \clr
44 mtc0 t0, CP0_STATUS
45 .set noreorder
46 sll zero, 3 # ehb
47 .set pop
48 .endm
49
50 .set noreorder
51
52 .globl _start
53 .text
54_start:
55 .org 0x000
56 b reset
57 nop
58 .org 0x080
59 b romReserved
60 nop
61 .org 0x100
62 b romReserved
63 nop
64 .org 0x180
65 b romReserved
66 nop
67 .org 0x200
68 b romReserved
69 nop
70 .org 0x280
71 b romReserved
72 nop
73 .org 0x300
74 b romReserved
75 nop
76 .org 0x380
77 b romReserved
78 nop
79 .org 0x480
80 b romReserved
81 nop
82
83 /*
84 * We hope there are no more reserved vectors!
85 * 128 * 8 == 1024 == 0x400
86 * so this is address R_VEC+0x400 == 0xbfc00400
87 */
88 .org 0x500
89 .align 4
90reset:
91
92 /* Clear watch registers */
93 dmtc0 zero, CP0_WATCHLO
94 dmtc0 zero, CP0_WATCHHI
95
96 /* WP(Watch Pending), SW0/1 should be cleared */
97 mtc0 zero, CP0_CAUSE
98
99 setup_c0_status ST0_KX 0
100
101 /* Init Timer */
102 mtc0 zero, CP0_COUNT
103 mtc0 zero, CP0_COMPARE
104
105#ifndef CONFIG_SKIP_LOWLEVEL_INIT
106 /* CONFIG0 register */
107 dli t0, CONF_CM_UNCACHED
108 mtc0 t0, CP0_CONFIG
109#endif
110
111 /* Initialize $gp */
112 bal 1f
113 nop
114 .dword _gp
1151:
116 ld gp, 0(ra)
117
118#ifndef CONFIG_SKIP_LOWLEVEL_INIT
119 /* Initialize any external memory */
120 dla t9, lowlevel_init
121 jalr t9
122 nop
123
124 /* Initialize caches... */
125 dla t9, mips_cache_reset
126 jalr t9
127 nop
128
129 /* ... and enable them */
130 dli t0, CONFIG_SYS_MIPS_CACHE_MODE
131 mtc0 t0, CP0_CONFIG
132#endif
133
134 /* Set up temporary stack */
135 dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
136 dla sp, 0(t0)
137
138 dla t9, board_init_f
139 jr t9
140 nop
141
142/*
143 * void relocate_code (addr_sp, gd, addr_moni)
144 *
145 * This "function" does not return, instead it continues in RAM
146 * after relocating the monitor code.
147 *
148 * a0 = addr_sp
149 * a1 = gd
150 * a2 = destination address
151 */
152 .globl relocate_code
153 .ent relocate_code
154relocate_code:
155 move sp, a0 # set new stack pointer
156
157 dli t0, CONFIG_SYS_MONITOR_BASE
158 dla t3, in_ram
159 ld t2, -24(t3) # t2 <-- uboot_end_data
160 move t1, a2
161 move s2, a2 # s2 <-- destination address
162
163 /*
164 * Fix $gp:
165 *
166 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
167 */
168 move t8, gp
169 dsub gp, CONFIG_SYS_MONITOR_BASE
170 dadd gp, a2 # gp now adjusted
171 dsub s1, gp, t8 # s1 <-- relocation offset
172
173 /*
174 * t0 = source address
175 * t1 = target address
176 * t2 = source end address
177 */
178
179 /*
180 * Save destination address and size for dlater usage in flush_cache()
181 */
182 move s0, a1 # save gd in s0
183 move a0, t1 # a0 <-- destination addr
184 dsub a1, t2, t0 # a1 <-- size
185
1861:
187 lw t3, 0(t0)
188 sw t3, 0(t1)
189 daddu t0, 4
190 ble t0, t2, 1b
191 daddu t1, 4
192
193 /* If caches were enabled, we would have to flush them here. */
194
195 /* a0 & a1 are already set up for flush_cache(start, size) */
196 dla t9, flush_cache
197 jalr t9
198 nop
199
200 /* Jump to where we've relocated ourselves */
201 daddi t0, s2, in_ram - _start
202 jr t0
203 nop
204
205 .dword _gp
206 .dword _GLOBAL_OFFSET_TABLE_
207 .dword uboot_end_data
208 .dword uboot_end
209 .dword num_got_entries
210
211in_ram:
212 /*
213 * Now we want to update GOT.
214 *
215 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
216 * generated by GNU ld. Skip these reserved entries from relocation.
217 */
218 ld t3, -8(t0) # t3 <-- num_got_entries
219 ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
220 ld t9, -40(t0) # t9 <-- _gp
221 dsub t8, t9 # compute offset
222 dadd t8, t8, gp # t8 now holds relocated _G_O_T_
223 daddi t8, t8, 16 # skipping first two entries
224 dli t2, 2
2251:
226 ld t1, 0(t8)
227 beqz t1, 2f
228 dadd t1, s1
229 sd t1, 0(t8)
2302:
231 daddi t2, 1
232 blt t2, t3, 1b
233 daddi t8, 8
234
235 /* Clear BSS */
236 ld t1, -24(t0) # t1 <-- uboot_end_data
237 ld t2, -16(t0) # t2 <-- uboot_end
238 dadd t1, s1 # adjust pointers
239 dadd t2, s1
240
241 dsub t1, 8
2421:
243 daddi t1, 8
244 bltl t1, t2, 1b
245 sd zero, 0(t1)
246
247 move a0, s0 # a0 <-- gd
248 dla t9, board_init_r
249 jr t9
250 move a1, s2
251
252 .end relocate_code
253
254 /* Exception handlers */
255romReserved:
256 b romReserved