wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2000 |
| 3 | * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. |
| 4 | * |
| 5 | * (C) Copyright 2004 |
| 6 | * ARM Ltd. |
| 7 | * Philippe Robin, <philippe.robin@arm.com> |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 28 | /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 29 | |
| 30 | #include <common.h> |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 31 | #include <watchdog.h> |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 32 | #include <asm/io.h> |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 33 | #include "serial_pl01x.h" |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 34 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 35 | /* |
| 36 | * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1 |
| 37 | * Integrator CP has two UARTs, use the first one, at 38400-8-N-1 |
| 38 | * Versatile PB has four UARTs. |
| 39 | */ |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 40 | #define CONSOLE_PORT CONFIG_CONS_INDEX |
wdenk | da04a8b | 2004-08-02 23:22:59 +0000 | [diff] [blame] | 41 | static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS; |
| 42 | #define NUM_PORTS (sizeof(port)/sizeof(port[0])) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 43 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 44 | static void pl01x_putc (int portnum, char c); |
| 45 | static int pl01x_getc (int portnum); |
| 46 | static int pl01x_tstc (int portnum); |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 47 | unsigned int baudrate = CONFIG_BAUDRATE; |
| 48 | DECLARE_GLOBAL_DATA_PTR; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 49 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 50 | #ifdef CONFIG_PL010_SERIAL |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 51 | |
| 52 | int serial_init (void) |
| 53 | { |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 54 | unsigned int divisor; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 55 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 56 | /* First, disable everything */ |
| 57 | writel(0x0, port[CONSOLE_PORT] + UART_PL010_CR); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 58 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 59 | /* Set baud rate */ |
| 60 | switch (baudrate) { |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 61 | case 9600: |
| 62 | divisor = UART_PL010_BAUD_9600; |
| 63 | break; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 64 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 65 | case 19200: |
| 66 | divisor = UART_PL010_BAUD_9600; |
| 67 | break; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 68 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 69 | case 38400: |
| 70 | divisor = UART_PL010_BAUD_38400; |
| 71 | break; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 72 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 73 | case 57600: |
| 74 | divisor = UART_PL010_BAUD_57600; |
| 75 | break; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 76 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 77 | case 115200: |
| 78 | divisor = UART_PL010_BAUD_115200; |
| 79 | break; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 80 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 81 | default: |
| 82 | divisor = UART_PL010_BAUD_38400; |
| 83 | } |
| 84 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 85 | writel(((divisor & 0xf00) >> 8), port[CONSOLE_PORT] + UART_PL010_LCRM); |
| 86 | writel((divisor & 0xff), port[CONSOLE_PORT] + UART_PL010_LCRL); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 87 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 88 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
| 89 | writel((UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN), |
| 90 | port[CONSOLE_PORT] + UART_PL010_LCRH); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 91 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 92 | /* Finally, enable the UART */ |
| 93 | writel((UART_PL010_CR_UARTEN), port[CONSOLE_PORT] + UART_PL010_CR); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 94 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 95 | return 0; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 98 | #endif /* CONFIG_PL010_SERIAL */ |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 99 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 100 | #ifdef CONFIG_PL011_SERIAL |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 101 | |
| 102 | int serial_init (void) |
| 103 | { |
| 104 | unsigned int temp; |
| 105 | unsigned int divider; |
| 106 | unsigned int remainder; |
| 107 | unsigned int fraction; |
| 108 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 109 | /* First, disable everything */ |
| 110 | writel(0x0, port[CONSOLE_PORT] + UART_PL011_CR); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 111 | |
| 112 | /* |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 113 | * Set baud rate |
| 114 | * |
| 115 | * IBRD = UART_CLK / (16 * BAUD_RATE) |
| 116 | * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE)) |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 117 | */ |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 118 | temp = 16 * baudrate; |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 119 | divider = CONFIG_PL011_CLOCK / temp; |
| 120 | remainder = CONFIG_PL011_CLOCK % temp; |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 121 | temp = (8 * remainder) / baudrate; |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 122 | fraction = (temp >> 1) + (temp & 1); |
| 123 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 124 | writel(divider, port[CONSOLE_PORT] + UART_PL011_IBRD); |
| 125 | writel(fraction, port[CONSOLE_PORT] + UART_PL011_FBRD); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 126 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 127 | /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */ |
| 128 | writel((UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN), |
| 129 | port[CONSOLE_PORT] + UART_PL011_LCRH); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 130 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 131 | /* Finally, enable the UART */ |
| 132 | writel((UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE), |
| 133 | port[CONSOLE_PORT] + UART_PL011_CR); |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 134 | |
| 135 | return 0; |
| 136 | } |
| 137 | |
Andreas Engel | 0813b12 | 2008-09-08 14:30:53 +0200 | [diff] [blame] | 138 | #endif /* CONFIG_PL011_SERIAL */ |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 139 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 140 | void serial_putc (const char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 141 | { |
| 142 | if (c == '\n') |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 143 | pl01x_putc (CONSOLE_PORT, '\r'); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 144 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 145 | pl01x_putc (CONSOLE_PORT, c); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 146 | } |
| 147 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 148 | void serial_puts (const char *s) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 149 | { |
| 150 | while (*s) { |
| 151 | serial_putc (*s++); |
| 152 | } |
| 153 | } |
| 154 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 155 | int serial_getc (void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 156 | { |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 157 | return pl01x_getc (CONSOLE_PORT); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 158 | } |
| 159 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 160 | int serial_tstc (void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 161 | { |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 162 | return pl01x_tstc (CONSOLE_PORT); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 163 | } |
| 164 | |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 165 | void serial_setbrg (void) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 166 | { |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 167 | baudrate = gd->baudrate; |
| 168 | serial_init(); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 169 | } |
| 170 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 171 | static void pl01x_putc (int portnum, char c) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 172 | { |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 173 | /* Wait until there is space in the FIFO */ |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 174 | while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_TXFF) |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 175 | WATCHDOG_RESET(); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 176 | |
| 177 | /* Send the character */ |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 178 | writel(c, port[portnum] + UART_PL01x_DR); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 179 | } |
| 180 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 181 | static int pl01x_getc (int portnum) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 182 | { |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 183 | unsigned int data; |
| 184 | |
| 185 | /* Wait until there is data in the FIFO */ |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 186 | while (readl(port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE) |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 187 | WATCHDOG_RESET(); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 188 | |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 189 | data = readl(port[portnum] + UART_PL01x_DR); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 190 | |
| 191 | /* Check for an error flag */ |
| 192 | if (data & 0xFFFFFF00) { |
| 193 | /* Clear the error */ |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 194 | writel(0xFFFFFFFF, port[portnum] + UART_PL01x_ECR); |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 195 | return -1; |
| 196 | } |
| 197 | |
| 198 | return (int) data; |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 199 | } |
| 200 | |
Andreas Engel | 8043861 | 2008-09-08 10:17:31 +0200 | [diff] [blame] | 201 | static int pl01x_tstc (int portnum) |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 202 | { |
Stuart Wood | 26136ef | 2008-06-02 16:42:19 -0400 | [diff] [blame] | 203 | WATCHDOG_RESET(); |
Matt Waddel | d6ce53e | 2010-10-07 15:48:46 -0600 | [diff] [blame] | 204 | return !(readl(port[portnum] + UART_PL01x_FR) & |
wdenk | c35ba4e | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 205 | UART_PL01x_FR_RXFE); |
wdenk | 4989f87 | 2004-03-14 15:06:13 +0000 | [diff] [blame] | 206 | } |