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git01.mediatek.com / filogic / uboot / eaed1986e77c1a0df49d96d80a79ddf19d13c4d9 / . / include / configs / mt7628.h
blob: 9df2715fc7dc0bbfb8f35b53a5c2d4d0762e4266 [file] [log] [blame]
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7628_H
9#define __CONFIG_MT7628_H
10
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]11#define CFG_SYS_SDRAM_BASE 0x80000000
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]12
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]13#define CFG_SYS_INIT_SP_OFFSET 0x80000
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]14
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]15/* Serial SPL */
Simon Glassf4d60392021-08-08 12:20:12 -0600[diff] [blame]16#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)
Tom Rinidf6a2152022-11-16 13:10:28 -0500[diff] [blame]17#define CFG_SYS_NS16550_CLK 40000000
18#define CFG_SYS_NS16550_COM1 0xb0000c00
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]19#endif
20
21/* Serial common */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]22#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]23 230400, 460800, 921600 }
24
25/* SPL */
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]26
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]27#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]28
29/* Dummy value */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]30#define CFG_SYS_UBOOT_BASE 0
developer7305b4c2020-04-21 09:28:49 +0200[diff] [blame]31
32#endif /* __CONFIG_MT7628_H */