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Shengzhou Liue6fb7702014-11-24 17:11:54 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11
12
13static u8 serdes_cfg_tbl[][4] = {
Shengzhou Liuea2310f2014-12-17 15:38:13 +080014 [0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
Shengzhou Liue6fb7702014-11-24 17:11:54 +080015 [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
16 [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
17 [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
18 [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
19 [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
20 [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
21 [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
22 [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
23 [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
Shengzhou Liuea2310f2014-12-17 15:38:13 +080024 [0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
Shengzhou Liue6fb7702014-11-24 17:11:54 +080025 [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
26 [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
27 [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
28 SGMII_2500_FM1_DTSEC1},
29 [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
30 [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
31 SGMII_2500_FM1_DTSEC1},
32 [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
33 [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
34};
35
36enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
37{
38 return serdes_cfg_tbl[cfg][lane];
39}
40
41int is_serdes_prtcl_valid(int serdes, u32 prtcl)
42{
43 int i;
44
45 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
46 return 0;
47
48 for (i = 0; i < 4; i++) {
49 if (serdes_cfg_tbl[prtcl][i] != NONE)
50 return 1;
51 }
52
53 return 0;
54}