blob: 7dc8385aa6a59297d5ac067c00696cbb2bc16074 [file] [log] [blame]
Shengzhou Liue6fb7702014-11-24 17:11:54 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11
12
13static u8 serdes_cfg_tbl[][4] = {
14 [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
15 [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
16 [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
17 [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
18 [0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
19 [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
20 [0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
21 [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
22 [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
23 [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
24 [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
25 [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
26 SGMII_2500_FM1_DTSEC1},
27 [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
28 [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
29 SGMII_2500_FM1_DTSEC1},
30 [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
31 [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
32};
33
34enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
35{
36 return serdes_cfg_tbl[cfg][lane];
37}
38
39int is_serdes_prtcl_valid(int serdes, u32 prtcl)
40{
41 int i;
42
43 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
44 return 0;
45
46 for (i = 0; i < 4; i++) {
47 if (serdes_cfg_tbl[prtcl][i] != NONE)
48 return 1;
49 }
50
51 return 0;
52}