Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 1 | /* |
SRICHARAN R | 8d24292 | 2012-03-12 19:49:32 +0000 | [diff] [blame] | 2 | * |
| 3 | * Common layer for reset related functionality of OMAP based socs. |
| 4 | * |
| 5 | * (C) Copyright 2012 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Sricharan R <r.sricharan@ti.com> |
Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 28 | #include <config.h> |
SRICHARAN R | 8d24292 | 2012-03-12 19:49:32 +0000 | [diff] [blame] | 29 | #include <asm/io.h> |
| 30 | #include <asm/arch/cpu.h> |
| 31 | #include <linux/compiler.h> |
Minkyu Kang | ae6f0c6 | 2009-07-20 11:40:01 +0900 | [diff] [blame] | 32 | |
SRICHARAN R | 8d24292 | 2012-03-12 19:49:32 +0000 | [diff] [blame] | 33 | void __weak reset_cpu(unsigned long ignored) |
| 34 | { |
| 35 | writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); |
| 36 | } |
Lokesh Vutla | e89f154 | 2012-05-29 19:26:41 +0000 | [diff] [blame^] | 37 | |
| 38 | u32 __weak warm_reset(void) |
| 39 | { |
| 40 | return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); |
| 41 | } |